11.4.2.5 Peripheral Clock Masking

It is possible to disable or enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock Mask registers (AHBMASK and APBxMASK) to ‘0’ and ’1’, respectively. The default state of the peripheral clocks is given by the peripheral bit Reset value in the AHBMASK and APBxMASK registers.

When the APB clock is not supplied to a peripheral, its registers cannot be read or written. The peripheral can be re-enabled by setting the corresponding mask bit to ‘1’.

Some peripherals may be connected to multiple clock domains (for instance, AHB and APB), in which case it will have several mask bits.

Clocks must be switched off only if it is certain that the peripheral will not be used: Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash memory. Switching off the clock to the MCLK peripheral (which contains the mask registers) or the corresponding APBx bridge will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system Reset.