27.4.2.1.1 Input Pin Configuration

To use pin Pxn as an input, the Input Buffer Enable bit in the Pin Configuration register (PINCFG[n].INEN) must be ‘1’ and bit n in the Data Direction register (DIR) must be ‘0’. The physical pin state can be read from the corresponding bit in the Data Input Value register (IN).

The pin will float if no external pull is connected and the Pull Enable bit in the Pin Configuration register (PINCFG[n].PULLEN) is ‘0’.

Figure 27-3. I/O Configuration - Standard Input

When the Pull Enable bit is ‘1’, pull-up is enabled when the corresponding OUT value is written to ‘1’.

Figure 27-4. I/O Configuration - Input With Pull

To reduce power consumption, the input synchronizer is clocked only when an input read is requested. This will delay the read operation by two cycles of the PORT clock. To eliminate the delay, the input synchronizers for each PORT group of eight pins can be configured to be always active. This is enabled by writing a ‘1’ to the corresponding bit in the Input Sampling Mode bit field of the Control register (CTRL.SAMPLING).