27.6 Register Summary

Tip:

The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a base address at byte address (PORT + 0x80 * group index) (A corresponds to group index 0, B to 1, etc.).

Within that set of registers, the pin index is y, from 0 to 31. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	DIR	7:0	DIR7	DIR6	DIR5	DIR4	DIR3	DIR2	DIR1	DIR0
		15:8	DIR15	DIR14	DIR13	DIR12	DIR11	DIR10	DIR9	DIR8
		23:16	DIR23	DIR22	DIR21	DIR20	DIR19	DIR18	DIR17	DIR16
		31:24	DIR31	DIR30	DIR29	DIR28	DIR27	DIR26	DIR25	DIR24
0x04	DIRCLR	7:0	DIR7CLR	DIR6CLR	DIR5CLR	DIR4CLR	DIR3CLR	DIR2CLR	DIR1CLR	DIR0CLR
		15:8	DIR15CLR	DIR14CLR	DIR13CLR	DIR12CLR	DIR11CLR	DIR10CLR	DIR9CLR	DIR8CLR
		23:16	DIR23CLR	DIR22CLR	DIR21CLR	DIR20CLR	DIR19CLR	DIR18CLR	DIR17CLR	DIR16CLR
		31:24	DIR31CLR	DIR30CLR	DIR29CLR	DIR28CLR	DIR27CLR	DIR26CLR	DIR25CLR	DIR24CLR
0x08	DIRSET	7:0	DIR7SET	DIR6SET	DIR5SET	DIR4SET	DIR3SET	DIR2SET	DIR1SET	DIR0SET
		15:8	DIR15SET	DIR14SET	DIR13SET	DIR12SET	DIR11SET	DIR10SET	DIR9SET	DIR8SET
		23:16	DIR23SET	DIR22SET	DIR21SET	DIR20SET	DIR19SET	DIR18SET	DIR17SET	DIR16SET
		31:24	DIR31SET	DIR30SET	DIR29SET	DIR28SET	DIR27SET	DIR26SET	DIR25SET	DIR24SET
0x0C	DIRTGL	7:0	DIR7TGL	DIR6TGL	DIR5TGL	DIR4TGL	DIR3TGL	DIR2TGL	DIR1TGL	DIR0TGL
		15:8	DIR15TGL	DIR14TGL	DIR13TGL	DIR12TGL	DIR11TGL	DIR10TGL	DIR9TGL	DIR8TGL
		23:16	DIR23TGL	DIR22TGL	DIR21TGL	DIR20TGL	DIR19TGL	DIR18TGL	DIR17TGL	DIR16TGL
		31:24	DIR31TGL	DIR30TGL	DIR29TGL	DIR28TGL	DIR27TGL	DIR26TGL	DIR25TGL	DIR24TGL
0x10	OUT	7:0	OUT7	OUT6	OUT5	OUT4	OUT3	OUT2	OUT1	OUT0
		15:8	OUT15	OUT14	OUT13	OUT12	OUT11	OUT10	OUT9	OUT8
		23:16	OUT23	OUT22	OUT21	OUT20	OUT19	OUT18	OUT17	OUT16
		31:24	OUT31	OUT30	OUT29	OUT28	OUT27	OUT26	OUT25	OUT24
0x14	OUTCLR	7:0	OUT7CLR	OUT6CLR	OUT5CLR	OUT4CLR	OUT3CLR	OUT2CLR	OUT1CLR	OUT0CLR
		15:8	OUT15CLR	OUT14CLR	OUT13CLR	OUT12CLR	OUT11CLR	OUT10CLR	OUT9CLR	OUT8CLR
		23:16	OUT23CLR	OUT22CLR	OUT21CLR	OUT20CLR	OUT19CLR	OUT18CLR	OUT17CLR	OUT16CLR
		31:24	OUT31CLR	OUT30CLR	OUT29CLR	OUT28CLR	OUT27CLR	OUT26CLR	OUT25CLR	OUT24CLR
0x18	OUTSET	7:0	OUT7SET	OUT6SET	OUT5SET	OUT4SET	OUT3SET	OUT2SET	OUT1SET	OUT0SET
		15:8	OUT15SET	OUT14SET	OUT13SET	OUT12SET	OUT11SET	OUT10SET	OUT9SET	OUT8SET
		23:16	OUT23SET	OUT22SET	OUT21SET	OUT20SET	OUT19SET	OUT18SET	OUT17SET	OUT16SET
		31:24	OUT31SET	OUT30SET	OUT29SET	OUT28SET	OUT27SET	OUT26SET	OUT25SET	OUT24SET
0x1C	OUTTGL	7:0	OUT7TGL	OUT6TGL	OUT5TGL	OUT4TGL	OUT3TGL	OUT2TGL	OUT1TGL	OUT0TGL
		15:8	OUT15TGL	OUT14TGL	OUT13TGL	OUT12TGL	OUT11TGL	OUT10TGL	OUT9TGL	OUT8TGL
		23:16	OUT23TGL	OUT22TGL	OUT21TGL	OUT20TGL	OUT19TGL	OUT18TGL	OUT17TGL	OUT16TGL
		31:24	OUT31TGL	OUT30TGL	OUT29TGL	OUT28TGL	OUT27TGL	OUT26TGL	OUT25TGL	OUT24TGL
0x20	IN	7:0	IN7	IN6	IN5	IN4	IN3	IN2	IN1	IN0
		15:8	IN15	IN14	IN13	IN12	IN11	IN10	IN9	IN8
		23:16	IN23	IN22	IN21	IN20	IN19	IN18	IN17	IN16
		31:24	IN31	IN30	IN29	IN28	IN27	IN26	IN25	IN24
0x24	CTRL	7:0	SAMPLING7	SAMPLING6	SAMPLING5	SAMPLING4	SAMPLING3	SAMPLING2	SAMPLING1	SAMPLING0
		15:8	SAMPLING15	SAMPLING14	SAMPLING13	SAMPLING12	SAMPLING11	SAMPLING10	SAMPLING9	SAMPLING8
		23:16	SAMPLING23	SAMPLING22	SAMPLING21	SAMPLING20	SAMPLING19	SAMPLING18	SAMPLING17	SAMPLING16
		31:24	SAMPLING31	SAMPLING30	SAMPLING29	SAMPLING28	SAMPLING27	SAMPLING26	SAMPLING25	SAMPLING24
0x28	WRCONFIG	7:0	PINMASK[7:0]
		15:8	PINMASK[15:8]
		23:16				SLEWLIM		PULLEN	INEN	PMUXEN
		31:24	HWSEL	WRPINCFG		WRPMUX	PMUX[3:0]
0x2C	EVCTRL	7:0	PORTEI0	EVACT0[1:0]		PID0[4:0]
		15:8	PORTEI1	EVACT1[1:0]		PID1[4:0]
		23:16	PORTEI2	EVACT2[1:0]		PID2[4:0]
		31:24	PORTEI3	EVACT3[1:0]		PID3[4:0]
0x30	PMUX[0]	7:0	PMUXO[3:0]				PMUXE[3:0]
...
0x3F	PMUX[15]	7:0	PMUXO[3:0]				PMUXE[3:0]
0x40	PINCFG[0]	7:0				SLEWLIM		PULLEN	INEN	PMUXEN
...
0x5F	PINCFG[31]	7:0				SLEWLIM		PULLEN	INEN	PMUXEN