27.4.2.1 I/O Pin Configuration
The I/O pins of the device are controlled by the PORT peripheral registers. Each port pin has a corresponding bit in the Data Direction (DIR) and Data Output Value (OUT) registers to configure it as an input or output, and to control the output or pull state.
The Pin Configuration register (PINCFG[n]) is used for additional I/O pin configuration. A pin can be set to a totem-pole or pull configuration.
Since pull configuration is done through the PINCFG[n] register, all intermediate PORT states during switching of the pin direction and pin values are avoided.
The I/O pin configurations summarized in the following table are described in detail in this chapter.
| DIR | INEN | PULLEN | OUT | Configuration |
|---|---|---|---|---|
| 0 | 0 | 0 | X | All digital disabled |
| 0 | 1 | 0 | X | Input without pull |
| 0 | 1 | 1 | 1 | Input with pull-up |
| 0 | 0 | 1 | 1 | Pull-up output; input buffer disabled |
| 1 | 0 | X | X | Drive output; input buffer disabled |
| 1 | 1 | X | X | Drive output; input buffer enabled |