1 Pinout I/O Descriptions

Table 1-1. Pinout I/O Descriptions
Pin Name⁽¹⁾	Pin Type	Buffer Type	PPS	Description
AD1AN0 - AD1AN4 AD1ANN1 - AD1ANN2 AD2AN0 - AD2AN5 AD2ANN1 - AD2ANN2 AD3AN0 - AD3AN5 AD3ANN1 - AD3ANN2 AD4AN0 - AD4AN5 AD4ANN1 - AD4ANN2 AD5AN0 - AD5AN4 AD5ANN1 - AD5ANN2	I I I I I I I I I I	Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog	No No No No No No No No No No	ADC1 positive input channels ADC1 negative input channels ADC2 positive input channels ADC2 negative input channels ADC3 positive input channels ADC3 negative input channels ADC4 positive input channels ADC4 negative input channels ADC5 positive input channels ADC5 negative input channels
ADTRG31	I	ST	Yes	ADC trigger input 31
CLKI CLKO	I O	ST/CMOS —	No No	External Clock (EC) source input. Always associated with OSCI pin  function. Oscillator crystal output. Connects to the crystal or resonator in Crystal Oscillator mode. Optionally, it functions as CLKO in RC and EC modes. Always associated with OSCO pin function.
CVDTX0-CVDTX31	O	—	No	CVD = Capacitive voltage divider for the integrated touch controller. CVDTX is the driven capacitive pin.
CVDAN0-CVDAN31	I	Analog	No	Analog input for the integrated touch controller.
OSCI OSCO	I I/O	ST/CMOS —	No No	Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to the crystal or resonator in Crystal Oscillator mode. Optionally, it functions as CLKO in RC and EC modes.
REFCLKI	I	ST	Yes	Reference clock input
REFCLKO	O	—	Yes	Reference clock output
INT0 INT1 INT2 INT3 INT4	I I I I I	ST ST ST ST ST	No Yes Yes Yes Yes	External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4
IOCA[15:0] IOCB[15:0] IOCC[15:0] IOCD[15:0] IOCE[10:0] IOCF[3:0], IOCF[11:5] IOCG[2:0], IOCG[9:4] IOCH[2:0]	I I I I I I I I	ST ST ST ST ST ST ST ST	No No No No No No No No	Interrupt-on-Change input for PORTA Interrupt-on-Change input for PORTB Interrupt-on-Change input for PORTC Interrupt-on-Change input for PORTD Interrupt-on-Change input for PORTE Interrupt-on-Change input for PORTF Interrupt-on-Change input for PORTG Interrupt-on-Change input for PORTH
IOMAD[11:0] IOMBD[11:0] IOMAF[11:0] IOMBF[11:0]	O I I I	ST ST ST ST	Yes Yes Yes Yes	I/O Monitor Bank A reference I/O Monitor Bank B reference I/O Monitor Bank A feedback I/O Monitor Bank B feedback
QEIA1 QEIB1 QEINDX1 QEIHOM1 QEICMP	I I I I O	ST ST ST ST —	Yes Yes Yes Yes Yes	QEI Input A1 QEI Input B1 QEI Index 1 input QEI Home 1 input QEI comparator output
RA0-RA15	I/O	ST	No	PORTA is a bidirectional I/O port
RB0-RB15	I/O	ST	No	PORTB is a bidirectional I/O port
RC0-RC15	I/O	ST	No	PORTC is a bidirectional I/O port
RD0-RD15	I/O	ST	No	PORTD is a bidirectional I/O port
RE0-RE15	I/O	ST	No	PORTE is a bidirectional I/O port
RF0-RF15	I/O	ST	No	PORTF is a bidirectional I/O port
RG[2:0], RG[9:4]	I/O	ST	No	PORTG is a bidirectional I/O port
RH[2:0]	I/O	ST	No	PORTH is a bidirectional I/O port
T1CK	I	ST	Yes	Timer1 external clock input
U1CTS U1RTS U1RX U1TX U1DSR U1DTR	I O I O I O	ST — ST — ST —	Yes Yes Yes Yes Yes Yes	UART1 clear-to-send UART1 request-to-send UART1 receive UART1 transmit UART1 data-set-ready UART1 data-terminal-ready
U2CTS U2RTS U2RX U2TX U2DSR U2DTR	I O I O I O	ST — ST — ST —	Yes Yes Yes Yes Yes Yes	UART2 clear-to-send UART2 request-to-send UART2 receive UART2 transmit UART2 data-set-ready UART2 data-terminal-ready
U3CTS U3RTS U3RX U3TX U3DSR U3DTR	I O I O I O	ST — ST — ST —	Yes Yes Yes Yes Yes Yes	UART3 clear-to-send UART3 request-to-send UART3 receive UART3 transmit UART3 data-set-ready UART3 data-terminal-ready
SENT1 SENT2 SENT1OUT SENT2OUT	I I O O	ST ST — —	Yes Yes Yes Yes	SENT1 input SENT2 input SENT1 output SENT2 output
PTGTRG24 PTGTRG25	O O	— —	Yes Yes	PTG trigger output 24 PTG trigger output 25
TCKI1-TCKI9 ICM1-ICM9 OCFA-OCFD OCM1-OCM9	I I I O	ST ST — —	Yes Yes Yes Yes	SCCP/MCCP timer inputs 1 through 9 SCCP/MCCP capture tnputs 1 through 9 SCCP/MCCP Fault inputs A through D SCCP/MCCP compare outputs 1 through 9
SCK1 SDI1 SDO1 SS1	I/O I O I/O	ST ST — ST	Yes Yes Yes Yes	Synchronous serial clock I/O for SPI1 SPI1 data in SPI1 data out SPI1 Client synchronization or frame pulse I/O
SCK2 SDI2 SDO2 SS2	I/O I O I/O	ST ST — ST	Yes Yes Yes Yes	Synchronous serial clock I/O for SPI2 SPI2 data in SPI2 data out SPI2 Client synchronization or frame pulse I/O
SCK3 SDI3 SDO3 SS3	I/O I O I/O	ST ST — ST	Yes Yes Yes Yes	Synchronous serial clock I/O for SPI3 SPI3 data in SPI3 data out SPI3 Client synchronization or frame pulse I/O
SCL1 SDA1 ASCL1 ASDA1	I/O I/O I/O I/O	ST ST ST ST	No No No No	Synchronous serial clock I/O for I2C1 Synchronous serial data I/O for I2C1 Alternate synchronous serial clock I/O for I2C1 Alternate synchronous serial data I/O for I2C1
SCL2 SDA2 ASCL2 ASDA2	I/O I/O I/O I/O	ST ST ST ST	No No No No	Synchronous serial clock I/O for I2C2 Synchronous serial data I/O for I2C2 Alternate synchronous serial clock I/O for I2C2 Alternate synchronous serial data I/O for I2C2
BISS1SL BISS1GS	I I	ST ST	Yes Yes	BiSS1 return input BiSS1 get sense
BISS1MO BISS1MA	O O	ST ST	Yes Yes	BiSS1 output BiSS1 clock
TMS TCK TDI TDO	I I I O	ST ST ST —	No No No No	JTAG test mode select pin JTAG test clock input pin JTAG test data input pin JTAG test data output pin
PCI8-PCI18 PCI19-PCI22 PWMEA-PWMEF PWM1L-PWM8L PWM1H-PWM8H APWM1L-APWM4L APWM1H-APWM4H	I I O O O O O	ST ST — — — — —	Yes Yes Yes Yes Yes Yes Yes	PWM PCI inputs 8 through 18 PWM PCI inputs 19 through 22 PWM event outputs A through F PWM low outputs 1 through 8 PWM high outputs 1 through 8 APWM low outputs 1 through 4 APWM high outputs 1 through 4
CLCINA-CLCIND CLC1OUT-CLC8OUT	I O	ST —	Yes Yes	CLC inputs A through D CLC outputs 1 through 8
CMP1A-CMP8A CMP1B-CMP8B CMP1C-CMP8C CMP1D-CMP5D CMP7D-CMP8D CMPNC-CMPNF CMPP	I I I I I I I	Analog Analog Analog Analog Analog Analog Analog	No No No No No No No	Comparator channels 1A through 8A inputs Comparator channels 1B through 8B inputs Comparator channels 1C through 8C inputs Comparator channels 1D through 5D inputs Comparator channels 7D through 8D inputs All comparators negative inputs All comparators positive input
DACOUT1 DACOUT2	O O	— —	No No	DAC1 output voltage DAC2 output voltage
IBIAS3, IBIAS2, IBIAS1, IBIAS0/ISRC3, ISRC2, ISRC1, ISRC0	O	Analog	No	Constant-Current outputs 0 through 3
OA1IN+ OA1IN- OA1OUT OA2IN+ OA2IN- OA2OUT OA3IN+ OA3IN- OA3OUT	I I O I I O I I O	— — — — — — — — —	No No No No No No No No No	Op Amp 1 positive input Op Amp 1 negative input Op Amp 1 output Op Amp 2 positive input Op Amp 2 negative input Op Amp 2 output Op Amp 3 positive input Op Amp 3 negative input Op Amp 3 output
UREF	O	—	No	UREF output
PGD1 PGC1 PGD2 PGC2 PGD3 PGC3	I/O I I/O I I/O I	ST ST ST ST ST ST	No No No No No No	Data I/O pin for programming/debugging communication channel 1 Clock input pin for programming/ debugging communication  channel 1 Data I/O pin for programming/ debugging communication channel 2 Clock input pin for programming/ debugging communication  channel 2 Data I/O pin for programming/ debugging communication channel 3 Clock input pin for programming/ debugging communication channel 3
MCLR	I/P	ST	No	Master clear (Reset) input. This pin is an active-low Reset to the device.
AV_DD	P	P	No	Positive supply for analog modules. This pin must be connected at all times.
AV_SS	P	P	No	Ground reference for analog modules. This pin must be connected at all times.
V_DD	P	—	No	Positive supply for peripheral logic and I/O pins
V_SS	P	—	No	Ground reference for logic and I/O pins
V_DDCORE	P	—	No	Positive supply for core logic. This is 1.1V
SWV_DD	P	—	No	Positive supply for buck regulator circuit
SWV_SS	P	—	No	Ground reference for buck regulator circuit
L_X	P	—	No	Switching pin to inductor for buck regulator circuit
Legend: CMOS = CMOS compatible input or output; Analog = Analog input; P = Power; ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; PPS = Peripheral Pin Select; TTL = TTL input buffer Note: Not all pins are available in all package variants. See the Pin Diagrams section for pin availability.