5 Memory Organization

This section describes the Memory Organization and Bus Matrix (BMX) in dsPIC33A devices. The following features are covered.

  • Memory and SFR Maps
  • Modified Harvard Architecture
  • Unified Memory Map
  • Split Data Bus Speeds
  • Bus Matrix:
    • Establishes communication between initiator and targets.
    • Decodes addresses and provides arbitration between multiple initiators requesting access to the same target.
    • Provides concurrent accesses to multiple targets from different initiators.
    • Generates a bus error exception back to an initiator on any failed access.
    • Provides support for the CPU to execute from RAM.