11 Interrupt Controller

The dsPIC33AK512MPS512 family interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to its CPU. The core supports a prioritized interrupt and trap exception scheme.

The interrupt controller has the following features:

  • Interrupt Vector Table (IVT) for User Memory
  • Reset Vector (Not Part of IVT)
  • Eight Processor Traps
  • Four Generic Traps + One Software Trap
  • Seven User Selectable Priority Levels
  • A Unique Vector for Each Interrupt or Exception in Full IVT Mode
  • A Collapsed Vector for All Peripheral Interrupts
  • Fixed Priority Within a Specified User Priority Level
  • Software Can Generate Any Peripheral Interrupt
  • Relocatable IVT (via IVTBASE Register)
  • Support for Testability via INTTREG