4.3.6.1 Vector Fail Address (VFA)

A bus error may occur when reading a vector location, which can result in an incorrect vector value being returned. To prevent the CPU from executing a Program Flow Control (PFC) instruction to an invalid address, the CPU detects this situation, sets the Vector Fail flag (SR.VF) in the Status Register and substitutes a register-based address as the vector address value.

This substitute address is stored in the Vector Fail Address (VFA) Special Function Register (SFR) within the CPU. Users should initialize the VFA to point to the Bus Error handler or a dedicated Bus Error handler. By default, the CPU initializes the VFA to the reset (first instruction) address during the reset sequence, ensuring a valid default value if the user does not set it.

Vector substitution only occurs in the case of a vector fetch bus error, making this a special type of bus error. The CPU does not generate a Bus Error trap request for the Interrupt Controller. However, it does raise its Interrupt Priority Level (IPL) to that of the Bus Error trap (IPL 14), rather than updating the IPL based on the Interrupt Controller’s input. If the VFA contains the Bus Error trap vector address, exception processing continues and enters the Bus Error handler, abandoning the original exception (which remains pending).

The Interrupt Controller records the failed exception's Interrupt Level Register (ILR) and Vector Number Register (VNR) in the INTTREG register as usual, since the CPU does not issue a Bus Error trap request. The Bus Error handler can use this information to determine the appropriate response if the SR.VF bit is set. If the handler determines the vector failure was temporary, it can safely return, allowing the pending exception to be retried. Otherwise, the handler should take further action as defined by the user. The stacked SR.VF bit will be clear, so executing RETFIE from the handler will automatically clear the bit.

If vector fetch bus errors do not need to be handled differently, ignore the SR.VF bit and treat the event as a standard bus error.

Alternatively, if the VFA register is left at its default reset address, a bus error during vector fetch will raise the CPU IPL to IPL 14 and vector to the application reset address. This does not reset the device, but the user can check the SR.VF bit during initialization. If it is set, the user may reset the device by executing a RESET instruction.