17.1 Device-Specific Information

Table 17-1. ADC Summary Table
Number of CoresMax Number of ChannelsMax Input ClockClock SourcePeripheral Bus Speed
516See Electrical Characteristics (ADC)CLKGEN6Fast (1:1 of CPU Clock)

The number of available positive and negative analog inputs is dependent on package size, as shown in the ADC External Input Availability table.

Table 17-2. ADC Clock Source Select bit (CLKSEL bits in ADxCON2 Register)
ValueDescription
1Standard (1:2 of CPU Clock)
0Clock Generator 6
Table 17-3. ADC Input Availability
ADC Input48-Pin64-Pin80-Pin100-Pin128-Pin129-PinComments
AD1ANN0AVSS ADC 1 ground negative input 0 supporting Differential mode
AD1ANN1 xxxxxADC 1 negative input 1 supporting Differential mode
AD1ANN2xxxxxxADC 1 negative input 2 supporting Differential mode
AD1ANN3ReservedReserved
AD1AN0xxxxxxADC 1 positive input 0
AD1AN1xxxxxxADC 1 positive input 1
AD1AN2xxxxxxADC 1 positive input 2
AD1AN3xxxxxxADC 1 positive input 3
AD1AN4 xxxxxADC 1 positive input 4
AD1AN5ReservedReserved
AD1AN6Internal ADC 1 15/16*VDD reference input
AD1AN7Internal ADC 1 UREF input
AD2ANN0AVSS ADC 2 ground negative input 0 supporting Differential mode
AD2ANN1xxxxxADC 2 negative input 1 supporting Differential mode
AD2ANN2xxxxxxADC 2 negative input 2 supporting Differential mode
AD2ANN3ReservedReserved
AD2AN0xxxxxxADC 2 positive input 0
AD2AN1xxxxxxADC 2 positive input 1
AD2AN2xxxxxxADC 2 positive input 2
AD2AN3 xxxxxADC 2 positive input 3
AD2AN4 xxxxxADC 2 positive input 4
AD2AN5 xxxxADC 2 positive input 5
AD2AN6Internal ADC 2 15/16*VDD reference input
AD2AN7Internal ADC 2 UREF input
AD3ANN0AVSS ADC 3 ground negative input 0 supporting Differential mode
AD3ANN1 xxxxADC 3 negative input 1 supporting Differential mode
AD3ANN2xxxxxxADC 3 negative input 2 supporting Differential mode
AD3ANN3ReservedReserved
AD3AN0xxxxxxADC 3 positive input 0
AD3AN1xxxxxxADC 3 positive input 1
AD3AN2xxxxxxADC 3 positive input 2
AD3AN3xxxxADC 3 positive input 3
AD3AN4xxxADC 3 positive input 4
AD3AN5xxxxxxADC 3 positive input 5
AD3AN6Internal ADC 3 15/16*AVDD reference input
AD3AN7Internal ADC 3 UREF input
AD4ANN0AVSSADC 4 ground negative input 0 supporting Differential mode
AD4ANN1xxxxxxADC 4 negative input 1 supporting Differential mode
AD4ANN2xxxxxxADC 4 negative input 2 supporting Differential mode
AD4ANN3 ReservedReserved
AD4AN0xxxxxxADC 4 positive input 0
AD4AN1xxxxxxADC 4 positive input 1
AD4AN2xxxxxxADC 4 positive input 2
AD4AN3xxxxxxADC 4 positive input 3
AD4AN4 xxxxxADC 4 positive input 4
AD4AN5xxxxxxADC 4 positive input 5
AD4AN6Internal ADC 4 15/16*AVDD reference input
AD4AN7Internal ADC 4 UREF input
AD5ANN0AVSSADC 5 ground negative input 0 supporting Differential mode
AD5ANN1xxxxxxADC 5 negative input 1 supporting Differential mode
AD5ANN2 xxxxxADC 5 negative input 2 supporting Differential mode
AD5ANN3 ReservedReserved
AD5AN0xxxxxxADC 5 positive input 0
AD5AN1xxxxxxADC 5 positive input 1
AD5AN2 xxxxxADC 5 positive input 2
AD5AN3xxxxxxADC 5 positive input 3
AD5AN4xxxxxxADC 5 positive input 4
AD5AN5Internal ADC 5 Touch ADC input
AD5AN6Internal ADC 5 15/16*AVDD reference input
AD5AN7Internal ADC 5 UREF input
AD5AN8Internal ADC 5 VDDCORE input
Table 17-4. TRG1SRC Trigger Source Selection Bits
ValueDescription
111111-101000Reserved
100111SCCP8 trigger
100110SCCP7 trigger
100101SCCP6 trigger
100100SCCP5 trigger
100011SCCP4 trigger
100010SCCP3 trigger
100001SCCP2 trigger
100000SCCP1 trigger
011111ADTRG31 (PPS)
011110PTG trigger 12
011101MCCP9 trigger
011100CLC4 out
011011CLC3 out
011010ITC
011001APWM 4 ADC trigger 1
011000APWM 3 ADC trigger 1
010111APWM 2 ADC trigger 2
010110APWM 2 ADC trigger 1
010101APWM 1 ADC trigger 2
010100APWM 1 ADC trigger 1
010011PWM 8 ADC trigger 2
010010PWM 8 ADC trigger 1
010001PWM 7 ADC trigger 2
010000PWM 7 ADC trigger 1
001111PWM 6 ADC trigger 2
001110PWM 6 ADC trigger 1
001101PWM 5 ADC trigger 2
001100PWM 5 ADC trigger 1
001011PWM 4 ADC trigger 2
001010PWM 4 ADC trigger 1
001001PWM 3 ADC trigger 2
001000PWM 3 ADC trigger 1
000111PWM 2 ADC trigger 2
000110PWM 2 ADC trigger 1
000101PWM 1 ADC trigger 2
000100PWM 1 ADC trigger 1
000011-000010Reserved
000001Software trigger initiated by using the ADnSWTRG register.
000000 Triggers are disabled.
Table 17-5. TRG2SRC Trigger Source Selection Bits
ValueDescription
111111-101000Reserved
100111SCCP8 trigger
100110SCCP7 trigger
100101SCCP6 trigger
100100SCCP5 trigger
100011SCCP4 trigger
100010SCCP3 trigger
100001SCCP2 trigger
100000SCCP1 trigger
011111ADTRG31 (PPS)
011110PTG trigger 12
011101MCCP9 trigger
011100CLC4 out
011011CLC3 out
011010ITC
011001APWM 4 ADC trigger 1
011000APWM 3 ADC trigger 1
010111APWM 2 ADC trigger 2
010110APWM 2 ADC trigger 1
010101APWM 1 ADC trigger 2
010100APWM 1 ADC trigger 1
010011PWM 8 ADC trigger 2
010010PWM 8 ADC trigger 1
010001PWM 7 ADC trigger 2
010000PWM 7 ADC trigger 1
001111PWM 6 ADC trigger 2
001110PWM 6 ADC trigger 1
001101PWM 5 ADC trigger 2
001100PWM 5 ADC trigger 1
001011PWM 4 ADC trigger 2
001010PWM 4 ADC trigger 1
001001PWM 3 ADC trigger 2
001000PWM 3 ADC trigger 1
000111PWM 2 ADC trigger 2
000110PWM 2 ADC trigger 1
000101PWM 1 ADC trigger 2
000100PWM 1 ADC trigger 1
000011Conversion repeat timer trigger defined by RPTCNT[5:0] (ADnCON[23:18]) bits.
000010Immediate re-trigger request
000001Software trigger initiated by using the ADnSWTRG register.
000000 Triggers are disabled.