10.5 Effects of Reset
The Reset value for the Reset Control register, RCON, will depend on the type of device Reset, as indicated in Table 10-3.
| Condition | Program Counter | EXTR | SWR | WDTO | SLEEP | IDLE | CM | BOR | POR | PWRMR |
|---|---|---|---|---|---|---|---|---|---|---|
| Power-on Reset or MCLR set as POR | 0x00000000_0000 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| Brown-out Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | u | 1 | |
| MCLR Reset during Run Mode | 1 | u | u | u | u | u | u | u | u | |
| MCLR Reset during Idle Mode | 1 | u | u | u | 1 | u | u | u | u | |
| MCLR Reset during Sleep Mode | 1 | u | u | 1 | u | u | u | u | u | |
| Software Reset Command | u | 1 | u | u | u | u | u | u | u | |
| Configuration Word Mismatch Reset | u | u | u | u | u | 1 | u | u | u | |
| WDT Time-out Reset during Run Mode | u | u | 0 | u | u | u | u | u | u | |
| WDT Time-out Reset during Idle Mode | PC+2 | u | u | 0 | u | 1 | u | u | u | u |
| WDT Time-out Reset during Sleep Mode | u | u | 1 | 1 | u | u | u | u | u | |
| Interrupt Exit from Idle Mode | PC+2 or Interrupt Vector | u | u | u | u | 1 | u | u | u | u |
| Interrupt Exit from Sleep Mode | u | u | u | 1 | u | u | u | u | u | |
| Power Monitor Reset Event | 0x00000000_0000 | u | u | u | u | u | u | 1 | 1 | 1 |
Legend:
u = unchanged | ||||||||||
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Note: The Program Counter (PC) is loaded with PC + 2 if
the interrupt priority is less than or equal to the CPU interrupt priority
level. The PC is loaded with the hardware vector address if the interrupt
priority is greater than the CPU interrupt priority level.
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