1 Features

The PCIESS is a hard block and supports the following features:

  • PCIE 3.0 compliant with 2.5 and 5.0 Gbps line speeds
  • x1, x2, and x4 lane-support1
  • Endpoint support for up to six 32-bit or three 64-bit base address register (BAR)
  • Root port support for up to two 32-bit or one 64-bit BAR
  • Two fully-independent Direct Memory Access (DMA) engines with Scatter-Gather DMA (SGDMA) support
  • One virtual channel (VC)
  • Single-function capability
  • Maximum payload size (MPS) of up to 256 bytes
  • Advanced error reporting (AER) support
  • Integrated clock domain crossing (CDC) to support user-selected frequency
  • Lane reversal/polarity inversion
  • Legacy PCI power management
  • Endpoint hot-plug capability (not supported for root port)
  • Native active-state power management L0 and L1 support
  • Power management event (PME) message
  • Latency tolerance reporting (LTR)
  • 64-bit AXI master and slave interface to the FPGA fabric
  • End-to-end data integrity
1

Each device supports two PCIESS blocks, which shares four lanes within a transceiver block. This permits two x1 PCIESS or two x2 PCIESS that can run simultaneously, or one PCIESS that can run as x4 and the other PCIESS is left unused.