2 References

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For information about transmitter, receiver, and transceiver block generation, see PolarFire Family Transceiver User Guide.
For information about DRI, see PolarFire Family DRI User Guide.
For information about PolarFire SoC PCIe Root Port Linux reference design, see GitHub.
For information about PolarFire FPGA reference design, see PolarFire FPGA PCIe EndPoint DDR3L DDR4 Memory Controller Data Plane.
For information about MSS, see PolarFire SoC FPGA MSS Technical Reference Manual.
For information about design initialization, see PolarFire Family Device Power-Up and Resets User Guide.
For information about board design recommendations, see respective PolarFire FPGA Board Design User Guide or PolarFire SoC FPGA Board Design Guidelines User Guide.
For information about configuration registers, see respective PolarFire Device Register Map or PolarFire SoC Register Map.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.