14.5.3.1 Device Configuration

In Fast Flash Programming mode, the device is in a specific test mode. Only a certain set of pins is significant. The rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode. Other pins must be left unconnected.

The figure and table below provide details on the signals and power supplies used when FFPI is implemented.

Table 14-5. Signal Description List
Signal NamePIO LinesFunctionTypeActive LevelComments
Power
VDD3V3I/O Lines and Main Power Supplies InputPowerConnect to 3.3V
VBATBackup Area and Backup I/O Lines Power Supply InputPowerConnect to 3.3V
VDDCORECore Power Supply InputPowerConnect to 1.1V
VDDPLLPLL Power Supply InputPowerConnect to 1.1V
GNDGroundGroundConnect to GND
Clocks
XINPA29Main Clock InputInput3.3V Square wave signal from 10 to 50 MHz
Test
TSTTest Mode SelectInputHighMust be at high (3.3V) during power-up, then low (0V) after reset period.
JTAGSELJTAG Test Mode SelectInputHighMust be at high (3.3V) during power-up, then low (0V) after reset period.
PIO
#CMDPA8Valid command availableInputLowPulled-up input at reset
RESPPB26Error ResponseOutputPulled-up input at reset
RDYPB24

0: Device is busy

1: Device is ready for a new command

OutputHighPulled-up input at reset
#OEPA9

Output Enable (active low)

0: the host releases the DATA[15:0] lines and asks the target device to drive them

1: the host drives the DATA[15:0] lines

InputLowPulled-up input at reset
#VALIDPB25

When #OE is 0, #VALID is 0 if a valid data can by read by the host from DATA[15:0] and #VALID is 1 if the data on DATA[15:0] is not valid yet.

When #OE is 1, the target device rises #VALID to 1

OutputLowPulled-up input at reset
MODE0PA23Specifies DATA type InputPulled-up input at reset
MODE1PA24
MODE2PA25
DATA0PA4Bi-directional data busInput/OutputPulled-up input at reset
DATA1PA5
DATA2PA6
DATA3PA7
DATA4PB3
DATA5PB4
DATA6PB9
DATA7PB10
DATA8PB11
DATA9PB12
DATA10PC10
DATA11PC11
DATA12PC12
DATA13PC13
DATA14PC14
DATA15PC15