14.2.2.2 GPNVM[0]: Security Bit

The security bit is based on a specific general-purpose NVM bit (GPNVM bit 0).

When security is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP/JTAG-DP interface or through the FFPI, is forbidden. This ensures the confidentiality of the code programmed in the Flash.

This bit is enabled through the command “Set General Purpose NVM Bit” in EEFC_FCR.FCMD. Disabling the security bit can only be achieved by asserting the ERASE signal on pin PB2 at 1, and after a full Flash erase is performed.