29.4.3.2 Write Commands

‘Write Page’ (WP) and ‘Write Page and Lock’ (WPL) commands are used to program the Flash main area.

Only 0 values can be programmed using the Flash technology; 1 is the erased value. In order to program words in a page, the corresponding 4K block that the page belongs to must be erased. Other commands are also available to erase by block, by multiple blocks or by sector.

After programming one or several 512-byte pages, the entire lock region containing these pages can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using the WPL command.

Data to be programmed in the Flash must be written in an internal 512-byte latch buffer before writing the programming command in EEFC_FCR. Data can be written at their final destination address, as the latch buffer is mapped into the Flash memory address space and wraps around within this Flash address space.

Byte and half-word accesses to the latch buffer are not allowed. Only 32-bit word accesses are supported. If a single byte is to be written in a 32-bit word, the rest of the word must be written with ones.

32-bit words must be written continuously, in either ascending or descending order. Writing the latch buffer in a random order is not permitted. This prevents mapping a C-code structure to the latch buffer and accessing the data of the structure in any order. It is instead recommended to fill in a C-code structure in SRAM and copy it in the latch buffer in a continuous order.

Write operations in the latch buffer are performed with the number of wait states programmed for reading the Flash.

The latch buffer is automatically re-initialized, i.e., written with logical ‘1’, after execution of each programming command. However, after power-up, the latch buffer is not initialized. If only part of the page is to be written with user data, the remaining part must be erased (written with ‘1’).

The programming sequence is the following:

  1. Write the data to be programmed in the latch buffer, up to 512 bytes.
  2. Write the programming command in EEFC_FCR. This automatically clears the bit EEFC_FSR.FRDY.
  3. When Flash programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the SEFC is activated.

Three errors can be detected in EEFC_FSR after a programming sequence:

  • Command error: a wrong keyword was written in EEFC_FCR.
  • Lock error: the page to be programmed belongs to a locked region. A command must be run previously to unlock the corresponding region.
  • Flash error: when programming is completed, the WriteVerify test of the Flash memory fails.

Only one page can be programmed at a time. It is possible to program all the bits of a page (full page programming) or only some of the bits of the page (partial page programming).

Depending on the number of bits to be programmed within the page, the SEFC adapts the write operations required to program the Flash.

When a ‘Write Page’ (WP) command is issued, the SEFC starts the programming sequence and all the bits written at 0 in the latch buffer are cleared in the Flash memory array.

During programming, i.e., until EEFC_FSR.FDRY rises, any access to the Flash is stalled until the programming completes. To avoid stalling the processor, the code can be run out of the internal SRAM.

If the Flash has to be read while a programming is active, the Write command can be suspended by writing the Suspend (SUSP) command in EEFC_FCR.

Consequently, EEFC_FSR.FDRY rises together with EEFC_FSR.FLSUSP, indicating the programming command is suspended.

Only Read accesses from the Flash are allowed during a suspended command.

The suspended programming command can be later resumed by writing a Resume command (RES) in EEFC_FCR.

If the SUSP command is issued late in the programming, the programming command may simply finish but not be suspended as indicated by EEFC_FSR.FDRY rising but EEFC_FSR.FLSUSP staying low.

If the same Write command is suspended then resumed multiple times, it is recommended that after the RES command, the next SUSP command should be given not earlier than 5 µs.