15.4.5 Power-up, Power-down and SUPC Reset

The SUPC is reset (Backup area reset) by powering down the selected voltage source of VDDBU (VDD3V3 or VBAT).

As long as a Backup area reset is asserted, the system is in the following state:

• The SUPC is in reset state, and consequently,
• The VDDCORE core voltage regulator is off and the VDDCORE reset signal is asserted. The I/O pins default to their reset state as described in the section “Package and Pinout”.

The slow RC oscillator, powered by VDDBU, is off as long as VDDBU voltage remains low.

As soon as VDDBU voltage is valid, the SUPC exits reset state. Five slow RC oscillator cycles later, the SUPC enables the VDDCORE voltage regulator and the VDDCORE POR. When the output signal of this VDDCORE POR indicates a valid VDDCORE voltage for at least one slow RC oscillator cycle, the VDDCORE core logic reset signal is de-asserted and the Reset Controller (RSTC) de-asserts the downstream reset signals in the VDDCORE domain.

At power-down, the SUPC is reset and its configuration is immediately lost. Without any sequencing, the core voltage regulator is turned off, the core reset signal (vddcore_nreset) is asserted, the I/O configuration is lost (I/Os default to their reset state), the oscillators and PLLs are switched off. Considering the uncontrolled nature of this power-down, it is strongly recommended to have the device in an idle state before reaching VDDBU low voltage threshold.