15.4.3 Core Voltage Regulator and Low-Power Modes

The SUPC controls the embedded VDDCORE voltage regulator. It controls its power-up sequence to ensure an optimal load.

The user can switch off the voltage regulator, thus putting the device into Backup mode, by writing SUPC_CR.VROFF to 1.

If an external power supply is used, the device is put into Backup mode by writing SUPC_CR.SHDW to 1.

When the internal voltage regulator is not used and VDDCORE is externally supplied, the voltage regulator can be disabled by writing SUPC_MR.VREGDIS to 1. In this case, SUPC_EMR.COREBGEN must be set to 1 once the external VDDCORE is supplied.

This asserts the VDDCORE domain reset signal after the write resynchronization time, which lasts two slow clock cycles (worst case). Once the VDDCORE domain reset signal is asserted, the processor, coprocessor and the peripherals are stopped one slow clock cycle before the core power supply shuts off.