15.4.4 VDD3V3 Supply Monitor

The SUPC embeds a supply monitor which monitors the VDD3V3 rail.

The VDD3V3 supply monitor can be used to prevent the processor from falling into an unpredictable state if the main power supply drops below a certain level.

The threshold of the VDD3V3 supply monitor is programmable in the IOSMTH field of the Supply Monitor Mode register (SUPC_SMMR). Refer to the section “Electrical Characteristics”.

The VDD3V3 supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock periods, depending on the user selection. This is configured in the IOSMSMPL field in SUPC_SMMR.

Enabling the VDD3V3 supply monitor for such reduced times divides the typical supply monitor power consumption by factors of 2, 16 and 128, respectively, if continuous monitoring of the VDD3V3 power supply is not required.

A VDD3V3 supply monitor detection generates either a reset of the VDDCORE domain or a wake-up (exit from Backup mode). Generating a VDDCORE domain reset when a VDD3V3 supply monitor detection occurs is enabled by writing SUPC_SMMR.IOSMRSTEN=1.

Waking up the device when a VDD3V3 supply monitor event occurs can be enabled by writing IOSMWKEN=1 in the Backup Mode register (SUPC_BMR).

A VDD3V3 supply monitor under voltage event can trigger an interrupt by writing IOSMEV=1 in the Interrupt Enable register (SUPC_IER).

The SUPC provides the following status bit:

  • SUPC_SR.IOSMWS: The flag rises when a VDD3V3 supply monitor event triggers a wake-up of the system. This flag is a copy of IOSMWS in the Wakeup Status register (SUPC_WUSR) and thus is cleared when SUPC_WUSR is read.
  • SUPC_SR.IOSMRSTS: The flag rises when VDD3V3 supply monitor under voltage event triggers a VDDCORE reset. This flag is a copy of SUPC_WUSR.IOSMRSTS and thus is cleared when SUPC_WUSR is read.
  • SUPC_SR.IOSMS: VDD3V3 supply monitor output.
  • SUPC_SR.IOSMIS: The flag rises when VDD3V3 supply monitor under voltage event occurs. This flag is a copy of SUPC_ISR.IOSMEV and thus is cleared when the SUPC_ISR is read.
    Figure 15-2. VDD3V3 Supply Monitor Status Bit and Associated Interrupt