20.4 Processor Clock Controller

The PMC features a Processor Clock (CPU_CLK0) and a Coprocessor Clock (CPU_CLK1) controller that implements the processor Sleep mode. CPU_CLK0 can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while LPM is at ‘0’ in the Fast Start-up Mode register (PMC_FSMR).

CPU_CLK0 is enabled after a reset and is automatically re-enabled by any enabled interrupt. The processor Sleep mode is entered by disabling CPU_CLK0, which is automatically re-enabled by any enabled interrupt, or by the reset of the product. CPU_CLK1 is disabled after reset. It is up to the Core 0 application to enable CPU_CLK1. Similar to CPU_CLK0, CPU_CLK1 is automatically re-enabled by any enable instruction after execution of a WFI instruction.

When processor Sleep mode is entered, the current instruction is finished before CPU_CLK0 (and/or CPU_CLK1) is stopped, but this does not prevent data transfers from other hosts of the system bus.

The clock selection is done in PMC_CPU_CKR.CSS and PMC_CPU_CKR.CPCSS.

The prescaler is configured in PMC_CPU_CKR.PRES and PMC_CPU_CKR.CPPRES.

The Processor Clock Controller also generates the Main System Bus Clocks, MCKx, and a sub-division of this MCKx, MCKxDIVx. These clocks are distributed to peripherals, to the system bus and to matrices. See the table “Peripheral Identifiers” for Main System Bus Clocks used versus peripherals.

Only one of CSS/CPCSS and PRES/CPPRES fields can be modified at a time. When one of these parameters is modified, no other modification can be performed on these fields as long as the MCKRDY/CPMCKRDY status flags are low.

Any modification in CSS/CPCSS and PRES/CPPRES fields must never lead to generate a MCK frequency that is greater than the maximum allowed system frequency. When changing the source clock of the system to a faster clock, the fields must be modified using the following order: PRES/CPPRES and then CSS/CPCSS. When changing the source clock of the system to a slower clock, the fields must be modified using the following order: CSS/CPCSS and then PRES/CPPRES.

If the destination clock does not exist, the switching is not performed. The CPU_CLK0 and CPU_CLK1 keep running with the previous clock and the system must be reset to run correctly again.