20.15 Recommended Programming Sequence
Steps given below are a high-level PMC programming sequence to achieve CPU and Bus clock configuration. This sequence does not provide any specific use cases regarding clock source configuration, clock division, etc.
- If the Main crystal oscillator is not required, the PLL can be directly configured (Step 5.) else this oscillator must be started (Step 2.).
- Verify the existence and frequency value of the Main crystal oscillator following the sequence defined in Main Frequency Counter
- If the Main crystal oscillator is enabled and valid, the source of MAINCK can be switched to the Main crystal oscillator by writing CKGR_MOR.MOSCSEL to 1 else the PLL can be directly configured.
- Wait for the end of the MAINCK source switching by either polling the MOSCSELS or setting the corresponding interrupt
- Configure the PLLs by following the setup defined in Divider and Phase Lock Loop Programming (if not required, proceed to Step 6.):
- Configure the MCK0DIV, MCK0DIV2 and MCK1DIV division ratio by setting PMC_CPU_CKR.RATIO_MCK0DIV, PMC_CPU_CKR.RATIO_MCK0DIV2 and PMC_CPU_CKR.RATIO_MCK1DIV.
- Select the division ratio of CPU_CLK0 by setting PMC_CPU_CKR.PRES.
PRES is used to define the CPU_CLK0 and MCK0 prescaler. The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value.
- Wait for the end of the CPU_CLK0 ratio switching by either polling the MCKRDY or setting the corresponding interrupt.
- Select the source clock of CPU_CLK0 by setting PMC_CPU_CKR.CSS.
CSS is used to select the clock source of MCK0 and CPU_CLK0. By default, the selected clock source is MAINCK.
- Wait for the end of the CPU_CLK0 source switching by either polling the MCKRDY or setting the corresponding interrupt.
PMC_CPU_CKR must not be programmed in a single write operation.
Reconfiguring PRES and CSS fields must always be done by following the right order of operation described above (steps 6 to 11)
- Configure the Programmable clocks (PCKx):
PCKx are controlled via registers PMC_SCER, PMC_SCDR and PMC_SCSR.
PCKx can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Three PCKx can be used. PMC_SCSR indicates which PCKx is enabled. By default all PCKx are disabled.
PMC_PCKx registers are used to configure PCKx as described in SysTick Clock.
- Enable the peripheral and generic clocks:
Once all of the previous steps have been completed, the peripheral and generic clocks can be configured via PMC_PCR as described in Peripheral and Generic Clock Controller.