35.6.6.4.1 Memory Registers/Commands Access

To perform memory register/command accesses, QSPI_IFR.TFRTYP must be set to ‘0’.

If the frame does not contain any data (such as the WRITE ENABLE command) or if QSPI_IFR.SMRM is set to ‘1’, the user must first configure the address to send by writing QSPI_IAR.ADDR (in the case the frame contains an address field).

  • SMRM = 1

When QSPI_IFR.SMRM is set to ‘1’, accesses to the memory are triggered and controlled by QSPI registers.

QSPI_IAR.ADDR must be configured if the frame contains an address field.

QSPI_IFR.APBTFRTYP is used to define whether the access is a read access or a write access. Write frames are triggered by writing QSPI_TDR and read frames are triggered by setting QSPI_CR.STTFR. Each time a new transfer trigger is issued, an SPI transfer is performed with a byte size. Another byte is read each time QSPI_RDR is read (flag RDRF shows when a data can be read in QSPI_RDR) or written each time QSPI_TDR is written (flag TDRE shows when a new data can be written). The SPI transfer ends by writing QSPI_CR.LASTXFER. See Instruction Transmission Flow Diagram SMRM = 1 and TFRTYP = 0 (Memory Register Access) for details.

  • SMRM = 0

When QSPI_IFR.SMRM is set to ‘0’, accesses to the memory are triggered by performing an access in the QSPI memory space. The address of the instruction frame is defined by the address of the first data access in the QSPI memory space. The addresses of the next accesses are not used by the QSPI.

QSPI_WRACNT.NBWRA defines the number of bytes to be sent to the memory before QSPI_ISR.LWRA rises, which indicates that the last byte has been transmitted. QSPI_WRACNT.NBWRA is reset and begins counting after each start of the instruction frame. At each system bus access, an SPI transfer is performed with the same size. For example, a halfword system bus access leads to a 16-bit SPI transfer, and a byte system bus access leads to an 8-bit SPI transfer. A special case is an instruction frame with address field and no data. In this case the instruction frame is triggered by setting QSPI_CR.STTFR and QPI_IAR is used for the address field. See Instruction Transmission Flow Diagram SMRM = 0 and TFRTYP = 0 (Memory Register Access) for details.