35.6.6.4 Instruction Frame Transmission

If the instruction frame includes the instruction code and/or the option code, the user must configure the instruction code and/or the option code to send by writing the fields WRINST, WROPT, RDINST and RDOPT in the Write Instruction Code register (QSPI_WICR) and the Read Instruction Code register (QSPI_RICR). QSPI_WICR configures instruction code and option code for write accesses, and QSPI_RICR configures instruction code and option code for read accesses. If a frame is without data (QSPI_IFR.DATAEN = 0), then QSPI_WICR is used for instruction code and option code.

Then, the user must write QSPI_IFR to configure the instruction frame depending on which instruction must be sent.

The instruction frame is configured by the following bits and fields of QSPI_IFR:

• WIDTH field—used to configure which data lanes are used to send the instruction code, the address, the option code and to transfer the data.
• INSTEN bit—used to enable the send of an instruction code.
• ADDREN bit—used to enable the send of an address after the instruction code.
• OPTEN bit—used to enable the send of an option code after the address.
• DATAEN bit—used to enable the transfer of data (READ or PROGRAM instruction).
• OPTL field—used to configure the option code length. The value written in OPTL must be consistent with the value written in the field WIDTH. For example: OPTL = 0 (1-bit option code) is not consistent with WIDTH = 6 (option code sent with QuadSPI protocol, thus the minimum length of the option code is 4 bits).
• ADDRL bit—used to configure the address length.
• TFRTYP field—used to define which type of data transfer must be performed.
• CRM bit—used to enable the continuous read mode, see Continuous Read Mode.
• DDREN bit—used to configure the Double Data Rate mode; instruction code is still transmitted in Single Data Rate mode. Instruction code can be transmitted in DDR mode by writing a ‘1’ to QSPI_IFR.DDRCMDEN.
• NBDUM field—used to configure the number of dummy cycles when reading data from the serial Flash memory. Between the address/option and the data, with some instructions, dummy cycles are inserted by the serial Flash memory.
• SMRM bit—when TFRTYP = ‘0’, defines if instruction frame transmission is triggered by register accesses or QSPI memory space accesses.
• APBTFRTYP bit—used to define the APB register transfer to memory type (read or write) when QSPI_IFR.TFRTYP is written to ‘0’.
• DQSEN bit—used to define if the targeted memory supplies a DQS signal.
• DDRCMDEN bit—used to define if the instruction code must be sent in DDR mode when QSPI_IFR.DDREN bit is written to ‘1’.
• PROTTYP bit—used to define the QSPI protocol type.

See QSPI Instruction Frame Register.

For instruction frame transmission, memory array accesses are different from the memory register/command accesses, as well as from accesses using the peripheral bus interface or the system bus interface.