16.4.2.4 Coprocessor Reset Control

The reset of the coprocessor is managed by RSTC_MR.CPROCEN. If this bit is set to ‘1’, the reset of the coprocessor is de-asserted. When RSTC_MR.CPROCEN=0, the reset of the coprocessor is asserted.

The reset of the coprocessor’s peripherals is managed by RSTC_MR.CPEREN. When this bit is set to ‘1’, the reset is de-asserted and thus the subsystem is starting. When RSTC_MR.CPEREN=0, the reset is asserted.

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