1 PolarFire FPGA PCIe Root Port

This document describes the Root Port capabilities of the PolarFire FPGA PCIe controller using Mi-V soft processor. The PCIe Root Port capabilities like the enumeration of an Endpoint device, low-speed and high-speed data transfers are demonstrated using the PCIe Root Port Demo GUI application.

The demo design includes a Mi-V soft processor, which initiates PCIe control and data plane functions. For more information about the PCIe Root Port design implementation and the necessary blocks and IP cores instantiated in Libero SoC, see Demo Design.

The demo design can be programmed using any of the following options:

• Using the job file: To program the device using the job file provided along with the design files, see Setting Up the Demo.
• Using Libero SoC: To program the device using Libero SoC, see Libero Design Flow. Use this option when the demo design is modified.

To run the demo, perform the following steps:

• The Root Port demo design must be programmed on a PolarFire Evaluation board.
• The Endpoint demo design must be programmed on another PolarFire Evaluation board.
• Both the boards must be connected using a PCIe Adapter card.

For more information about setting up the PCIe Root Port demo, see Setting Up the Demo.