1.5 Reset Structure

The following figure shows the reset structure of the PCIe Root port demo design.

Figure 1-7. Reset Structure

The Reset_AXI_IF_0(CoreReset_PF) block synchronizes “PLL_LOCK” signal of PF_DDR4_SS_0 IP with the DDR4 system clock(200MHz) to generate FABRIC_RESET_N signal, which drives the PCIe_RP_0 and MIV_SS_0 blocks.

The Reset_MIV_0(CoreReset_PF) block synchronizes the external user_resetn (SW6 on the PolarFire Evaluation board) and DEVICE_INIT_DONE(PF_INIT_MONITOR) together with the RISCV system clock (80 MHz) to generate the SYS_RESET_N, which drives the PF_DDR4_SS block.

The CORERESET_PF_C0_0(CoreReset_PF) block synchronizes “CTRLR_READY” signal of PF_DDR4_SS_0 IP with the RISCV system clock (80 MHz) to generate FABRIC_RESET_N signal, which drives the PCIe_RP_0, MIV_SS_0.

For more information about device initialization, see PolarFire Family Power-Up and Resets User Guide.

For more information on CoreReset_PF IP core, see the CoreReset_PF Handbook from the Libero catalog.