7.3 Transceiver Connections

This section describes the typical transceiver to CoreTSE connections in BASE-T and BASE-X design.

The following table lists the transceiver input and output port connections.

Table 7-3. XCVR Port Connections
Port Name	Input or Output	Connection Description
CTRL_CLK	Input	40 MHz clock for the enhanced receiver management logic Can be sourced from the on-chip 160 MHz RC oscillator through a clock divider, or it can be connected to the output fabric clock of CCC.
CTRL_ARST_N	—	Input signal to reset ERM Drive this signal from the XCVR_INIT_DONE signal of the PF_INIT_MONITOR component.
CLKS_FROM_TX_PLL	—	XCVR transmit clock sourced from the TX PLL
LANE0_RXD_N LANE0_RXD_P	—	Differential receive input pads for receiving the Ethernet data
LANE0_CDR_REF_CLK	—	125 MHz reference for clock and data recovery
LANE0_PCS_ARST_N	—	Asynchronous active-low reset signal used to reset the PCS module of XCVR lane
LANE0_PMA_ARST_N	—	Asynchronous active-low reset signal used to reset the PMA module of XCVR lane
LANE0_RX_DATA [9:0]	—	The 10-bit RX data from XCVR to CoreTSE:RCG [9:0]
LANE0_TXD_N LANE0_TXD_P	—	Differential transmit output pads
LANE0_RX_CLK_R	—	Recovered regional receive clock from XCVR to the fabric logic and CoreTSE:TBI_RX_CLK
LANE0_TX_DATA [9:0]	—	The 10-bit TX data from CoreTSE:TCG [9:0] to XCVR

AN4623