28.8.8 DFLL48M Control B
| Name: | DFLLCTRLB |
| Offset: | 0x20 |
| Reset: | 0x00 |
| Property: | Read-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WAITLOCK | BPLCKC | QLDIS | CCDIS | USBCRM | LLAW | STABLE | MODE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – WAITLOCK Wait Lock
This bit controls the DFLL output clock, depending on lock status:
0: Output clock before the DFLL is locked.
1: Output clock when DFLL is locked (Fine lock).
Bit 6 – BPLCKC Bypass Coarse Lock
This bit controls the coarse lock procedure:
0: Bypass coarse lock is disabled.
1: Bypass coarse lock is enabled.
Bit 5 – QLDIS Quick Lock Disable
0: Quick Lock is enabled.
1: Quick Lock is disabled.
Bit 4 – CCDIS Chill Cycle Disable
0: Chill Cycle is enabled.
1: Chill Cycle is disabled.
Bit 3 – USBCRM USB Clock Recovery Mode
0: USB Clock Recovery Mode is disabled.
1: USB Clock Recovery Mode is enabled.
Bit 2 – LLAW Lose Lock After Wake
0: Locks will not be lost after waking up from sleep modes if the DFLL clock has been stopped.
1: Locks will be lost after waking up from sleep modes if the DFLL clock has been stopped.
Bit 1 – STABLE Stable DFLL Frequency
0: FINE calibration tracks changes in output frequency.
1: FINE calibration register value will be fixed after a fine lock.
Bit 0 – MODE Operating Mode Selection
0: The DFLL operates in open-loop operation.
1: The DFLL operates in closed-loop operation.