28.8.13 DPLL Ratio Control

Refer to the Synchronization section in the Clock System Overview chapter for details on the functionality of this register.

Name:	DPLLRATIO
Offset:	0x34 + n*0x14 [n=0..1]
Reset:	0x00000000
Property:	PAC Write-Protection, Write-Synchronized


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
				LDRFRAC[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
				LDR[12:8]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	LDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 20:16 – LDRFRAC[4:0] Loop Divider Ratio Fractional Part

Write these bits to set the fractional part of the frequency multiplier. Due to synchronization there is a delay between writing to DPLLnRATIO.LDRFRAC[4:0] and the effect on the DPLLn output clock. The value written DPLLnRATIO.LDRFRAC[4:0] will be read back immediately and the DPLLRATIO bit in the synchronization busy register, DPLLnSYNCBUSY.DPLLRATIO, will be set. DPLLnSYNCBUSY.DPLLRATIO will be cleared when the operation is completed.

Bits 12:0 – LDR[12:0] Loop Divider Ratio

Write these bits to set the integer part of the frequency multiplier. The value written DPLLnRATIO.LDR[3:0] will be read back immediately and the DPLLRATIO bit in the synchronization busy register, DPLLnSYNCBUSY.DPLLRATIO, will be set. DPLLnSYNCBUSY.DPLLRATIO will be cleared when the operation is completed.