51.9.6 Synchronization Busy
| Name: | SYNCBUSY |
| Offset: | 0x18 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RXDATA | TXDATA | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXEN | TXEN | CKEN1 | CKEN0 | ENABLE | SWRST | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 9 – RXDATA Rx Data Synchronization Status
This bit is cleared when the synchronization of the Rx DATA Holding (RXDATA) register between the clock domains is complete.
This bit is set when the synchronization of the Rx DATA Holding (RXDATA) register between the clock domains is started.
Bit 8 – TXDATA Tx Data Synchronization Status
This bit is cleared when the synchronization of the Tx DATA Holding (TXDATA) register between the clock domains is complete.
This bit is set when the synchronization of the Tx DATA Holding (TXDATA) register between the clock domains is started.
Bit 5 – RXEN Rx Serializer Enable Synchronization Status
This bit is cleared when the synchronization of the CTRLA.RXEN bit between the clock domains is complete.
This bit is set when the synchronization of the CTRLA.RXEN bit between the clock domains is started.
Bit 4 – TXEN Tx Serializer Enable Synchronization Status
This bit is cleared when the synchronization of the CTRLA.TXEN bit between the clock domains is complete.
This bit is set when the synchronization of the CTRLA.TXEN bit between the clock domains is started.
Bits 2, 3 – CKENx Clock Unit x Enable Synchronization Status [x=1..0]
Bit CKENx is cleared when the synchronization of the CTRLA.CKENx bit between the clock domains is complete.
Bit CKENx is set when the synchronization of the CTRLA.CKENx bit between the clock domains is started.
Bit 1 – ENABLE Enable Synchronization Status
This bit is cleared when the synchronization of the CTRLA.ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of the CTRLA.ENABLE bit between the clock domains is started.
Bit 0 – SWRST Software Reset Synchronization Status
This bit is cleared when the synchronization of the CTRLA.SWRST bit between the clock domains is complete.
This bit is set when the synchronization of the CTRLA.SWRST bit between the clock domains is started.