31.5.10 ADACQ

ADC Acquisition Time Control Register
Note: The individual bytes in this multibyte register can be accessed with the following register names:
  • ADACQH: Accesses the high byte ADACQ[12:8]
  • ADACQL: Accesses the low byte ADACQ[7:0]
Name: ADACQ
Offset: 0x1D21

Bit 15141312111098 
    ACQ[12:8] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
 ACQ[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 12:0 – ACQ[12:0] Acquisition (charge share time) Select

Table 31-8. Acquisition Time
ADACQ Acquisition Time
CS != ADCRCCS = ADCRC
1 1111 1111 11118191 clocks of FOSC8191 clocks of ADCRC
1 1111 1111 11108190 clocks of FOSC8190 clocks of ADCRC
1 1111 1111 11018189 clocks of FOSC8189 clocks of ADCRC
.........
0 0000 0000 00102 clocks of FOSC2 clocks of ADCRC
0 0000 0000 00011 clocks of FOSC1 clocks of ADCRC
0 0000 0000 0000Not included in the data conversion cycle(1)
Note:
  1. If ADPRE is not equal to ‘0’, then ACQ = 0 means Acquisition Time is 8192 clocks of FOSC or ADCRC.
The individual bytes in this multibyte register can be accessed with the following register names:ADACQH: Accesses the high byte ADACQ[12:8]ADACQL: Accesses the low byte ADACQ[7:0]