31.5.6 ADCLK
Note: ADC Clock divider
is only available if FOSC is selected as the ADC clock source (CS =
0
).Name: | ADCLK |
Offset: | 0x1D2D |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CS[5:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 5:0 – CS[5:0] ADC Clock divider Select
Value | Description |
---|---|
n | ADC Clock frequency = FOSC/(2*(n+1)) |