8.3 Hardware Debug

After the design works correctly in simulation, hardware debugging can be started. The first step is to ensure that the guidelines specified in PolarFire FPGA Board Design User Guide and PolarFire SoC FPGA Board Design User Guide are followed, see the References section. This section lists general checks that can be performed during hardware debug:

  • Verify that the parameters (timing, signal width, memory parts, and so on) entered in the configurator are correct.
  • Create a simple design that replicates the issue.
  • Ensure that all voltages on the board are correctly set and the noise is within the specified limits.
  • Ensure that all terminations are adequate.
  • Ensure that clock and reset signals are clean and correct.
  • Perform a Signal Integrity (SI) analysis. Key items to be observed during the analysis are:
    • Setup and hold time between data signals (DQ) and their respective DQS
    • Setup and hold time between control/command/address signals and the clock
    • Overshoot and undershoot of all signals with respect to JEDEC specifications
    • DC threshold multi-crossing because of excessive ringing
  • Cool and heat the device to understand whether temperature variations are affecting the functionality. Temperature fluctuations may uncover a timing-related issue.
  • Run the device at a lower speed. Ensure that the DDR clock frequency is set within the minimal operating frequency of the device.
  • Verify that the Libero SoC version and the DDR subsystem IP version are compatible.
  • Try debugging the design on a different board of the same revision.