Revision History

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The revision history table describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.


Revision	Date	Description
H	05/2025	The following is a summary of the changes made in this revision: Added Table 2-6 in ECC section. Added a note under Table 2-6. Changed the valid range of "CK/CA additive offset" configuration option to “0–7” in Configuring the DDR3 Subsystem, Configuring the LPDDR3 Subsystem and Configuring the DDR4 Subsystem. Removed the "ODT Activation Settings on Read" configuration options from Configuring the DDR3 Subsystem, Configuring the LPDDR3 Subsystem and Configuring the DDR4 Subsystem. Updated the assertion behavior of the Reinitialization Control signal (CTRLR_INIT) in Table 2-13 in DDR Subsystem Ports, Configuring the DDR3 Subsystem, Configuring the LPDDR3 Subsystem and Configuring the DDR4 Subsystem. Added a note under Table 2-26 to describe a high-level recommensation on synchronizing the ARST_N signal of the PF_IOD_OCTAL_DDR IP. Updated the note in PolarFire Board Design Recommendations. Added a note under Figure 6-8 and Figure 7-8 to describe a high-level guideline for using an optimal termination resistor (R_T) value. Updated a note describing that DQ bit swapping within a nibble is supported in PolarFire Board Design Recommendations and PolarFire SoC Board Design Recommendations. Updated a note under Place and Route Pin-out-Rules. Added a note regarding the “CL118” warning generated during the synthesis of PF_DDR4 memory controller. See Timing Constraints. Updated the example PDC command in Using PDC.
G	10/2024	The following is a summary of the changes made in this revision: Updated Configuring the DDR3 Subsystem as follows: Updated Figure 2-49 and Figure 2-51. Added CK/CA additive offset parameter information. Updated Configuring the LPDDR3 Subsystem as follows: Updated Figure 2-56 and Figure 2-57. Updated CK/CA additive offset parameter related information. Updated Configuring the DDR4 Subsystem as follows: Updated Figure 2-62 and Figure 2-63. Added CK/CA additive offset parameter information.
F	06/2024	The following is a summary of the changes made in this revision: Added footnote 2 under Table . Changed the section title from “Training Logic for Embedded DDR Controller” to Training Logic for the PolarFire SoC MSS DDR Controller . Added Maximum Density Supported by the PolarFire SoC MSS DDR Controller. Updated the description of the DM/DM_N port in Table 2-15. Added note regarding the tCCD_L timing parameter in Configuring the DDR4 Subsystem. Updated note in Configuring the DDR4 Subsystem. Updated Figure 2-15 and changed the value of L_B_SIZE from 32 to 128. Updated Figure 2-16, changed the value of L_B_SIZE from 32 to 128, and removed the last bullet point “L_R_VALID is deasserted”. Updated note regarding the DQS value in Octal DDR PHY-Only solution. Added note about disabling the TMR option during Synthesis, see Physical Constraints. Removed the text “(for fabric LPDDR3 memory controller)” next to CMD/ADDR to REF_CLK training in Training Logic because CK/CA additive offset field is applicable for all the other DDR types. Revised the note about the DQ bits swapping in PolarFire Board Design Recommendations and PolarFire SoC Board Design Recommendations. Changed CS, CKE, and ODT signals to single-bit and Bank Address to 3-bit (BA[2:0]) in Table 6-3. Removed the termination resistor value of “39_1%” in Figure 6-8, and replaced the value with a symbol “(R_T)”. Removed the termination resistor value of “39_1%” in Figure 7-8, and replaced the value with a symbol “(R_T)”.
E	06/2023	The following is a summary of the changes made in this revision: Changed the document title to PolarFire Family Memory Controller User Guide. Added RT PolarFire support. Updated MSS DDR Memory Controller and Hardware Probes mentioning that both LPDDR4 and DDR4 training issues are debugged using Memory Log Analyzer. Added a note under Table 2-9 mentioning the data limit to be ensured during DDR4 memory transfers using the AXI interface. Updated Octal DDR PHY-Only Solution by correcting that the Octal DDR PHY configurator supports up to four ranks per interface instead of two ranks. Updated the description of the I{INTERFACE#}R{RANK#}_{CLOCK}_DATA output port. Added information regarding the default value in the description of the Automatic ZQ Calibration Period (us) parameter in the DDR3, LPDDR3, and DDR4 configurator’s Memory Timing tab. Also, added a note describing that this default value is based on the preset configuration. See Configuring the DDR3 Subsystem, Configuring the LPDDR3 Subsystem, and Configuring the DDR4 Subsystem. Added a note in the description of the RESET_N signal. See Table 5-3.
D	10/2022	The following is a summary of the changes made in this revision: Added information about LPDDR4 initialization sequence. See LPDDR4 (For PolarFire SoC FPGA Only). Added board design recommendation for LPDDR4. See LPDDR4. Changed the QDR SRAM Address Width and SRAM_DATA_WIDTH naming as per the configurator. See Table 1. Updated the QDR address width information, see Features. In QDR Resource Utilization, removed the note that mentioned about the fixed address width, data width, and burst size in QDR RTL - Fast simulation mode.
C	08/2022	The following is a summary of the changes made in this revision: Added a note regarding SHIELD signals in Table 2-15. Added CMD/ADDR to REF_CLK training information specific to LPDDR3 in Training Logic. Added Configuring the LPDDR3 Subsystem and Configuring the DDR4 Subsystem to describe the PF_LPDDR3 and PF_DDR4 Configurator options separately. Updated QDR training information, see Training Logic. Added QDR Resource Utilization. Added information about the DQ bit swapping support, see PolarFire Board Design Recommendations and PolarFire SoC Board Design Recommendations. Added a note about DDR interface migration, see Appendix: Fabric DDR Placement Locations.
B	11/2021	The following is a summary of the changes made in this revision: Updated the clock frequency value of PolarFire Octal DDR PHY IP from 200 MHz to 250 MHz. See Octal DDR PHY-Only Solution and Table 1. Updated the description of the output signal DOFF_N of the QDR Controller, see Port List. Added RTL_Fast simulation information for QDR memory, see Configuring QDR Memory Controller IP and RTL_Fast Simulation. Updated Figure 2-43 to show the latest configuration parameter Enable Differential DQS and added this configuration parameter to Table 2-25. Added the `ALERT_N` signal and updated the description of the `stat_ca_parity_error` signal in Table 2-8. Updated the description of the `ALERT_N` signal in Table 8. Added the information about the Memory Format and Enable Parity/Alert options in General.
A	08/2021	The first publication of this document. This user guide was created by merging the following documents: UG0676: PolarFire FPGA Memory Controller User Guide UG0906: PolarFire SoC FPGA Memory Controller User Guide For more information, see Table and Table respectively.

The following revision history table describes the changes that were implemented in the UG0676: PolarFire FPGA Memory Controller User Guide document. The changes are listed by revision.

Note: UG0676: PolarFire FPGA Memory Controller User Guide document is now obsolete and the information in the document has been migrated to PolarFire® FPGA and PolarFire SoC FPGA Memory Controller User Guide.

Table . Revision History of UG0676: PolarFire FPGA Memory Controller User Guide
Revision	Date	Description
Revision 8.0	04/21	The following is a summary of the changes made in this revision. Updated that the DDR Controller complies with the AXI3/4 protocol. Added DDR4 Additional Controller Options. Added DDR4 Optimization Guidelines. Added the prerequisite of setting VDDI and VREF before placing the DDR subsystem. Removed DQ bit swapping information because it is not supported. Added information about the minimum operating frequency of LPDDR3. Updated for Libero SoC v2021.1.
Revision 7.0	10/20	The following is a summary of the changes made in this revision. Added information about Octal DDR PHY-Only Solution. Updated support for ECC at maximum width for various device variants. Added brief information about SmartDebug capability of displaying DDR training data. Updated for Libero SoC v12.5.
Revision 6.0	05/20	The following is a summary of the changes made in this revision. Updated the description of the QDR output port DOFF_N. Updated the QDR Training information. Updated QDR related information for Burst of 2.
Revision 5.0	04/19	The following is a summary of the changes made in this revision. Updated the document for Libero SoC v12.0. Added simulated timing waveforms for write and read sequence with and without lookahead precharge. Added simulated timing waveforms for sample multi-burst write and read sequence. Added simulated timing waveforms for sample SDRAM write and read sequence. Updated the information about the DQ bit swapping supported. Updated the table that lists the Write Data to Write Strobe Mapping for QDR x36 mode. Added tables that list the Write Data to Write Strobe Mapping for QDR x18 and x9 modes. Updated “Burst of 2 local interface timing” and “Burst of 4 local interface timing” diagrams in QDR Memory Controller. Updated the QDR simulation options. Added information about BFM simulation. Added L_D_REQ_LAST_P0 and L_R_VALID_LAST_P0 signals in “Native Interface Signals” table.
Revision 4.0	09/18	The following is a summary of the changes made in this revision. The document was updated for Libero SoC PolarFire v2.3. Added information about the DDR PHY-only solution. Removed the VREFDQ leveling step from the initialization sequence of DDR3 and DDR4.
Revision 3.0	04/18	The following is a summary of the changes made in this revision. Updated the title of the document and added the QDR memory controller information. Now, both DDR and QDR information is available in this document. Updated the Libero SoC PolarFire version to v2.1 throughout the document. Updated the DDR3 and DDR4 resource utilization data. Updated the information about connectivity between DDR3 and PolarFire devices. Updated the information about the native interface signals L_DATAIN[N:0], L_DATAOUT[N:0], and L_DM_IN[N:0]. Updated the data widths and I/O standard information for various types of memories. Added the information about the simulation options available in the DDR3 configurator. Updated the DDR3 and DDR4 parameters for PolarFire devices. Updated the information about the standard LPDDR3 and DDR3 device configurations. Added the DDR3, LPDDR3, and DDR4 layout guidelines. Added the list of DDR placement location for each device package. Removed the instances that mention the LPDDR2 support throughout the document.
Revision 2.0	06/17	The following is a summary of the changes made in this revision. Information about DDR memory interface data lanes was updated. Information about training logic was updated. Information about diagnostic options was updated. Information about physical constraints of the DDR subsystem was updated. Information about accessing DDR Subsystem using the native interface was updated.
Revision 1.0	02/17	The first publication of UG0676: PolarFire FPGA Memory Controller User Guide.

The following revision history table describes the changes that were implemented in the UG0906: PolarFire SoC FPGA Memory Controller User Guide document. The changes are listed by revision.

Note: UG0906: PolarFire SoC FPGA Memory Controller User Guide document is now obsolete and the information in the document has been migrated to PolarFire® FPGA and PolarFire SoC FPGA Memory Controller User Guide.

Table . Revision History of UG0906: PolarFire SoC FPGA Memory Controller User Guide
Revision	Date	Description
Revision 3.0	04/21	The following is a summary of the changes made in this revision. Updated that DDR Controller complies with the AXI3/4 protocol. Added DDR4 Additional Controller Options. Added DDR4 Optimization Guidelines. Added the prerequisite of setting VDDI and VREF before placing the DDR subsystem. Removed the DQ bit swapping information because it is not supported. Updated for Libero SoC v2021.1.
Revision 2.0	09/20	Updated for Libero SoC v12.5.
Revision 1.0	04/20	The first publication of the UG0906: PolarFire SoC FPGA Memory Controller User Guide.