6 PolarFire Board Design Recommendations

The GPIO and HSIO of PolarFire devices support various memory interfaces.

GPIO supports DDR3.
HSIO supports DDR4, DDR3, DDR3L, and LPDDR3.

The following table lists the various types of memories supported in PolarFire devices.

Table 6-1. DDR3, LPDDR3, DDR3L, and DDR4 Parameters
Parameter	DDR3	LPDDR3	DDR3L	DDR4
VDDIO	1.5V	1.2V	1.35V	1.2V
VTT, VREF	0.75V	0.6V	0.675V	0.6V
Clock, Address, and Command (CAC) Layout	Daisy Chained  (Fly-by)	Point to point	Daisy Chained (Fly-by)	Daisy Chained (Fly-by)
Data Strobe	Differential	Differential	Differential	Differential
ODT	Dynamic	Dynamic	Dynamic	Dynamic
Match Addr/CMD/Ctrl to Clock Tightly	Yes	Yes	Yes	Yes
Match DQ/DM/DQS Tightly	Yes	Yes	Yes	Yes
Match DQS to Clock Loosely	Not Required	Not Required	Not Required	Not Required
I/O Standard	SSTL_15	HSUL-12	SSTL_135	POD-12¹
RZQ	240_1%	240_1%	240_1%	240_1%

Note:

HSTL_12 IO standard is used for DDR4 address, command, and control signals.

For more information on DDR memories, see the following documents:

JESD79-3F JEDEC standard for DDR3 SDRAM specifications
JESD79-4 JEDEC standard for DDR4 SDRAM specifications
JESD209-3 JEDEC standard for LPDDR3 SDRAM specifications

Tip: DQ bit swapping within a nibble is supported for PCB routing flexibility between DDR controller and the DDR* memory. This must be done at PCB design, not by Libero I/O editor.