7 PolarFire SoC Board Design Recommendations

The GPIO and HSIO of PolarFire SoC devices support various memory interfaces.

  • GPIO supports DDR3.
  • HSIO supports DDR4, DDR3, DDR3L, LPDDR3, and LPDDR4.

The following table lists the various types of memories supported in PolarFire SoC devices.

Table 7-1. DDR3, LPDDR3, DDR3L, LPDDR4, and DDR4 Parameters
ParameterDDR3LPDDR3DDR3LDDR4LPDDR4
VDDIO1.5V1.2V 1.351.2V1.1V
VTT, VREF0.75V0.6V0.675V0.6V0.55V
Clock, Address, and Command (CAC) LayoutDaisy Chained 
(Fly-by)Point to pointDaisy Chained

(Fly-by)

Daisy Chained (Fly-by)Point-to-Point 2
Data StrobeDifferentialDifferentialDifferentialDifferentialDifferential
ODTDynamicDynamicDynamicDynamicDynamic
Match Addr/CMD/Ctrl to Clock TightlyYesYesYesYesYes
Match DQ/DM/DQS TightlyYesYesYesYesYes
Match DQS to Clock LooselyNot RequiredNot RequiredNot RequiredNot RequiredNot Required
I/O StandardSSTL_15HSUL-12SSTL_135POD-121LVSTL 1.1V
RZQ240_1%240_1%240_1%240_1%240_1%
Note:
  1. HSTL_12 IO standard is used for DDR4 address, command, and control signals.
  2. For dual channel, LPDDR4 needs to go with T-topology routing. For more information, see LPDDR4.

For more information on DDR memories, see the following documents:

  • JESD79-3F JEDEC standard for DDR3 SDRAM specifications
  • JESD79-4 JEDEC standard for DDR4 SDRAM specifications
  • JESD209-3 JEDEC standard for LPDDR3 SDRAM specifications
Tip: DQ bit swapping within a nibble is supported on the PCB for routing flexibility as follows:
  • Between the Fabric DDR controller and DDR3, DDR3L, LPDDR3, and DDR4 memories
  • Between the MSS DDR controller and DDR3, DDR3L, LPDDR3, and DDR4 memories