2 Fabric DDR Subsystem

The Fabric DDR subsystem is made up of the following soft and hard blocks:

  • PolarFire DDR controller (soft)
  • Training logic (soft)
  • I/O lane (hard)
  • Phase-Locked Loop (PLL) (hard)

The following memory interface solutions can be created as shown in the following figures:

  • Fabric DDR subsystem—consists of PolarFire DDR controller (PF_DDR IP), PLL, I/O lane, and training logic.
  • DDR PHY-Only solution—consists of PLL, I/O lane, and training logic. This solution is intended for third-party DDR controller implementations. This solution is supported only for DDR3, DDR3L, DDR4, and LPDDR3 memory devices.
  • Octal DDR PHY-Only Solution—I/O lane, IOD logic, PLL, and soft fabric logic. This solution is intended for memory devices which use an 8-bit serial interface in DDR mode. For example, xSPI (JESD251), HyperBUS, and ONFI.
Figure 2-1. Fabric DDR Subsystem
Figure 2-2. DDR PHY-Only Solution
Figure 2-3. Octal DDR PHY-Only Solution

The Fabric DDR subsystem accepts read and write commands using the AMBA Advanced Extensible Interface 4 (AXI3/4) or using a native interface. The subsystem translates the AXI interface commands for the off-chip DDR SDRAM. It can also automatically perform DDR initialization, refresh, and ZQ calibration functions.

The Fabric DDR subsystem and the PHY-Only solution can be configured using the DDR Configurator from Libero® System-on-Chip (SoC) > IP catalog. One of the two configuration modes can be selected:

  • Preset configuration—allows speed-based selection of memory devices for presetting memory initialization and timing parameters.
  • User configuration—allows manual configuration of memory initialization and timing parameters.