The following reference design has two reset domains. The CORERESET_PF_0 is connected to the
PF_CRYPTO and COREAHBL2AHBL_BRIDGE blocks. The CORERESET_PF_1 is connected to the
COREAHBL2AHBL_BRIDGE, MIV_RV32, SRAM_Buffer, LSRAM, Core_JTAG_Debug, CoreAHBLite, System
Services, and MIV_ESS blocks. The following figure shows the reset structure.Figure 4-3. Reset Structure
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