AN4591

11 Revision History

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The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Table 11-1. Revision History
Revision	Date	Description
D	03/2025	Added Appendix 3: Programming the Device Using FlashPro Express section.
C	02/2025	The following is the list of changes in revision C of the document: Updated the document for Libero v2024.2. Updated the `.job` filepath and TCL script filepath throughout the document. Updated Table 2-1 in the Design Requirements section. Updated Figure 4-1 in the Design Description section. Updated Figure 4-2 in the Clocking Structure section. Added Reset Structure section. Updated Hardware Implementation section as follows: Added MIV_ESS to Table 4-1. Added CoreGPIO_C0_0 and CORESPI_C0_0 to the Table 4-2. Updated Figure 4-5. Updated Figure 4-6 in the FPGA Resource Utilization section. Updated Figure 4-7, Figure 4-9 and Figure 4-10 in the Software Implementation section. Updated Figure 4-11 and Figure 4-12 in the Linker Script Update section. Updated Figure 8-1 in the Appendix 2: User Cryptoprocessor Simulation section.
B	04/2023	In User Cryptoprocessor updated the text from "RSA, DSA, and modular exponentiation (Diffie-Hellman) with key sizes up to 4096-bits" to "RSA, DSA, and modular exponentiation (Diffie-Hellman) with key sizes up to 3072-bits".
A	08/2022	The following is the list of changes in revision A of the document: The document was migrated to the Microchip template. The document number was updated from 51900464 to DS00004591. The document ID was updated from AC464 to AN4591. Updated Appendix 2: User Cryptoprocessor Simulation. Updated LSRAM Initialization from SPI Flash .
11.0	—	The following is a summary of the changes made in this revision. Updated LSRAM Initialization from SPI Flash. Updated Clocking Structure. Updated Figure 4-2. Updated Hardware Implementation. Updated Table 4-2. Updated Figure 4-5. Updated Figure 4-6. Updated Figure 4-15. Updated Figure 4-16. Updated Appendix 2: User Cryptoprocessor Simulation. Updated Figure 8-1. Updated Appendix 2: User Cryptoprocessor Simulation.
10.0	—	Added Appendix 4: Running the TCL Script.
9.0	—	In this revision, information about Prerequisites was updated.
8.0	—	The following is a summary of the changes made in this revision. Updated the document for Libero SoC v12.2. Removed the references to Libero version numbers. Added information about enabling protection for SPI Flash client. For more information, refer to LSRAM Initialization from SPI Flash.
7.0	—	The following is a summary of the changes made in this revision. Information about how to unlock the sNVM pages was added. See Adding a Dummy Client to Unlock the sNVM Pages. Updated the document for Libero SoC v12.1.
6.0	—	Updated the document for Libero SoC v12.0.
5.0	—	The document was updated for Libero SoC PolarFire v2.3 release.
4.0	—	The document was updated for Libero SoC PolarFire v2.2 release.
3.0	—	The document was updated for Libero SoC PolarFire v2.1 release.
2.0	—	The following is a summary of the changes made in this revision. Information about initializing the SRAM component with the HEX file was added, see LSRAM Initialization from SPI Flash. The document was updated to include features and enhancements introduced in the Libero SoC PolarFire v2.0 release.
1.0	—	Initial release.

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