4.3 Hardware Implementation
(Ask a Question)To build a Mi-V subsystem for PolarFire FPGAs, use the Libero SoC design suite to create an FPGA design using the Mi-V processor core and peripheral cores. The following table lists the IP cores used in the reference design.
| IP Core | Description |
|---|---|
| MIV_RV32 | Mi-V soft processor |
| Core_JTAG_DEBUG | Facilitates the connection of Joint Test Action Group (JTAG) compatible soft core processors to the JTAG header for debugging. It provides fabric access to the JTAG interface using the UJTAG macro. |
| PF_INIT_MONITOR | The System Controller uses this macro to check the status of device initialization. The device initialization includes SRAM initialization from µPROM, sNVM, or SPI Flash. The DEVICE_INIT_DONE signal is used as a reset. |
| CoreAHBLite | Multi-master AHB-Lite bus |
| COREAHBL2AHBL_BRIDGE | AHB to AHB bridge connects two AHB-Lite buses, clocked by asynchronous clocks. This is required because the User Cryptoprocessor clock is different from the rest of the Mi-V processor subsystem clock. |
| PF_CRYPTO | Macro to access hard User Cryptoprocessor |
| PF_SRAM_AHBL_AXI | PolarFire LSRAM; used as system memory for Mi-V processor. SRAM buffer; used as memory buffer for User Cryptoprocessor. |
| PF_CCC | Macro to access PolarFire Clock Conditioning Circuit (CCC) block. It is used to synthesize 80 MHz and 180 MHz clock frequencies from the CCC with an on-board 50 MHz reference clock. |
| PF_SYSTEM_SERVICES | The PF_SYSTEM_SERVICES provides access to the System Services supported by the PolarFire device. These are System Controller actions initiated from the user design, using the PF_SYSTEM_SERVICES. |
| MIV_ESS | Multi-featured, highly-configurable Extended SubSystem (ESS) which supports both bootstrap and base peripherals. It is specifically designed to use with MIV_RV32 soft processor. It has APB interface to access subsystem memory-mapped peripherals and other cores like SPI, GPIO and UART. |
To create a programming file, configure and connect the IP cores listed in Table 4-1 and then run the Libero design flow. For more information about how to build a Mi-V processor subsystem for PolarFire devices, see AN4997: PolarFire FPGA Building a Mi-V Processor Subsystem . This Mi-V processor subsystem can be extended to integrate a User Cryptoprocessor into the system.
The MIV_RV32 processor core comprises an instruction fetch unit, an execution pipeline, and a data memory system. In the Mi-V processor memory map, the 0x8000_0000 to 0x8FFF_FFFF range is defined for the AXI4 interface to access the LSRAM; the 0x7000_0000 to 0x7FFF_FFFF range is defined for the MIV_ESS's APB interface; and the 0x6000_0000 to 0x6FFF_FFFF range is defined for the AHBLite I/O interface. The MIV_RV32 processor's reset vector address is set to 0x80000000. The processor’s reset vector address is configurable. The MIV_RV32's reset is an active-low signal, which must be de-asserted in sync with the system clock through a reset synchronizer. For more information about the MIV_RV32 core, see MIV_RV32 User Guide from Libero Catalog.
The MIV_RV32 processor accesses the application execution memory using the AXI4 interface. The AXI4 bus interface is configured to provide a 256 MB memory slot beginning at the address 0x80000000. The PolarFire LSRAM memory block (LSRAM_0 instance) is connected to this slot, and the LSRAM acts as an application execution memory for the Mi-V processor.
The MIV_RV32 processor directs the data transactions between addresses 0x60000000 and 0x6FFF_FFFF to the AHBL interface. The AHBL interface is connected to the CoreAHBLite_0 bus to communicate with peripherals connected to its slave slots. The CoreAHBLite_0 bus instance is configured to provide 16 slave slots, each of size 64 KB. The sixteen 64 KB slots consume a total address space of 16 ✕ 64 ✕ 1024 = 2^20 bytes, and can be addressed using a 20-bit address bus. The CoreAHBLite_0 bus maps the connected peripherals within the address range, using only the lower 20-bits of the MMIO bus address.
The following table summarizes the memory map of the reference design.
| Component | Description | Memory Map |
|---|---|---|
| PF_CRYPTO_proc_0 | User Cryptoprocessor | 0x62000000 to 0x6200FFFF |
| PF_SYSTEM_SERVICES_C0_0 | System Services | 0x73000000 to 0x73FFFFFF |
| MIV_ESS_UART | UART peripheral | 0x71000000 to 0x71FFFFFF |
| SRAM_Buffer_0 | Memory buffer for User Cryptoprocessor | 0x61000000 to 0x61FFFFFF |
| MIV_ESS_GPIO | GPIO peripheral | 0x75000000 to 0x75FFFFFF |
| MIV_ESS_SPI | SPI peripheral | 0x76000000 to 0x76FFFFFF |
| LSRAM_0 | Mi-V processor system memory | 0x80000000 to 0x8FFFFFFF |
In this reference design, the User Cryptoprocessor clock (crypto_clk) is configured to operate at 180 MHz, and the clock for the rest of the Mi-V subsystem (sys_clk) operates at 80 MHz. This reference design uses the CoreAHBL2AHBL_Bridge IP to provide clock domain crossing between sys_clk and crypto_clk.
The CoreAHBL2AHBL_Bridge IP functions as a bridge between the AHB master and AHB slave, where master and slave operate in two clock domains that are asynchronous in nature. The following figure shows the CoreAHBL2AHBL_Bridge IP Configurator.
The CoreAHBL2AHBL_Bridge_0 is configured to connect the User Cryptoprocessor to the Mi-V processor peripheral bus for control and primary data input and output. In this configuration, the sys_clk must be connected to the bridge's slave interface clock (HCLK_S0), and the crypto_clk must be connected to the bridge's master interface clock (HCLK_M0).
The CoreAHBL2AHBL_Bridge_1 is configured to connect the User Cryptoprocessors AHB master port to the Mi-V processors peripheral bus for DMA transactions. In this configuration, the sys_clk must be connected to the bridge's master interface clock (HCLK_M0), and the crypto_clk must be connected to the bridge's slave interface clock (HCLK_S0).
The following figure shows the SmartDesign view of the Mi-V processor subsystem with a User Cryptoprocessor.
For more details on component configurations and connections, see the Libero project created using provided TCL scripts.