4.1 Clocking Structure
(Ask a Question)In the following reference design, there are two clock domains. The on-board 50 MHz crystal oscillator is connected to the PF_CCC block, which generates 80 MHz and 180 MHz clocks.
The 180 MHz crypto clock is connected to PF_CRYPTO and COREAHBL2AHBL_BRIDGE blocks.
The 80 MHz system clock is connected to COREAHBL2AHBL_BRIDGE, MIV_RV32, SRAM_Buffer, LSRAM, Core_JTAG_Debug, CoreAHBLite, System Services, and MIV_ESS blocks.
The following figure shows the clocking structure.
