74.6.5.2 QSPI Timings
For the QSPI0 instance, the timings shown in the tables below are provided
in the following domains:
- 1.8V domain: VDDQSPI0 from 1.7V to 1.9V, maximum external capacitor: 10 pF, drive: 01 (Type A)
- 3.3V domain: VDDQSPI0 from 3.0V to 3.6V, maximum external capacitor: 10 pF, drive: 01 (Type A)
For the QSPI1 instance, the timings shown in the table below are provided in the following
domains:
- 1.8V domain: VDDQSPI1 from 1.7V to 1.9V, maximum external capacitor: 10 pF, DRV: 1, SR: 1
- 3.3V domain: VDDQSPI1 from 3.0V to 3.6V, maximum external capacitor: 10 pF, DRV: 0, SR: 0
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| fQSCK | QSCK maximum frequency | – | – | 133 | MHz |
| QSPI0 | QIOx data in to QSCK falling edge (input setup time) | – | 1 | – | ns |
| QSPI1 | QIOx data in to QSCK falling edge (input hold time) | – | 1 | – | ns |
| QSPI2 | QSCK falling edge to QIOx delay | – | 0 | 2 | ns |
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| fQSPI | QSCK operating frequency | – | – | 57.7 | MHz |
| tQSCK_MIN | Minimum SPCK period | – | 17.3 | – | ns |
| QSPI6 | CS low before QSCK edge (rising or falling)(1) | – | 2.9 | – | ns |
| QSPI7 | QSCK edge (rising or falling) to CS high(2) | – | 5.7 | – | ns |
| QSPI8 | QIOx input data setup to QSCK edge (rising or falling) | – | 3.5 | – | ns |
| QSPI9 | QIOx input data hold after QSCK edge (rising or falling) | – | 1.0 | – | ns |
| QSPI10 | QSCK edge (rising or falling) to QIOx delay | – | -2.1 | 2.1 | ns |
Note:
- Refer to DLYCS and DLYBS descriptions in Quad Serial Peripheral Interface (QSPI) for more configuration details.
- Refer to DLYBCT description in Quad Serial Peripheral Interface (QSPI) for more configuration details.
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| fQSPI | QSCK operating frequency | – | – | 100.0 | MHz |
| tQSCK_MIN | Minimum SPCK period | – | 10.0 | – | ns |
| QSPI11 | CS low before QSCK edge (rising or falling)(1) | – | 4.5 | – | ns |
| QSPI12 | QSCK edge (rising or falling) to CS high(2) | – | 3.0 | – | ns |
| QSPI13 | QIOx input skew to DQS edge (rising or falling) | – | -1.2 | 1.2 | ns |
| QSPI14 | QSCK edge (rising or falling) to QIOx delay | tQSCK/4+ | -1.7 | 1.7 | ns |
Note:
- Refer to DLYCS and DLYBS descriptions in Quad Serial Peripheral Interface (QSPI) for more configuration details.
- Refer to DLYBCT description in Quad Serial Peripheral Interface (QSPI) for more configuration details.