46.9.3 SSC Receive Clock Mode Register

This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.

Name: SSC_RCMR
Offset: 0x10
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 PERIOD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 STTDLY[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
    STOPSTART[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
 CKG[1:0]CKICKO[2:0]CKS[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:24 – PERIOD[7:0] Receive Period Divider Selection

This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD + 1) Receive Clock.

Bits 23:16 – STTDLY[7:0] Receive Start Delay

If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the current start of reception. When the receiver is programmed to start synchronously with the transmitter, the delay is also applied.

Note: STTDLY must be configured in relation to the receive synchronization data to be stored in SSC_RSHR.

Bit 12 – STOP Receive Stop Selection

ValueDescription
0 After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0.
1 After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.

Bits 11:8 – START[3:0] Receive Start Selection

ValueNameDescription
0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
1 TRANSMIT Transmit start
2 RF_LOW Detection of a low level on RF signal
3 RF_HIGH Detection of a high level on RF signal
4 RF_FALLING Detection of a falling edge on RF signal
5 RF_RISING Detection of a rising edge on RF signal
6 RF_LEVEL Detection of any level change on RF signal
7 RF_EDGE Detection of any edge on RF signal
8 CMP_0 Compare 0

Bits 7:6 – CKG[1:0] Receive Clock Gating Selection

ValueNameDescription
0 CONTINUOUS None
1 EN_RF_LOW Receive Clock enabled only if RF Low
2 EN_RF_HIGH Receive Clock enabled only if RF High

Bit 5 – CKI Receive Clock Inversion

CKI affects only the Receive Clock and not the output clock signal.

ValueDescription
0 The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge.
1 The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge.

Bits 4:2 – CKO[2:0] Receive Clock Output Mode Selection

ValueNameDescription
0 NONE None, RK pin is an input
1 CONTINUOUS Continuous Receive Clock, RK pin is an output
2 TRANSFER Receive Clock only during data transfers, RK pin is an output

Bits 1:0 – CKS[1:0] Receive Clock Selection

ValueNameDescription
0 MCK Divided Clock
1 TK TK Clock signal
2 RK RK pin