46.9.2 SSC Clock Mode Register

This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.

Name: SSC_CMR
Offset: 0x4
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     DIV[11:8] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 DIV[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 11:0 – DIV[11:0] Clock Divider

ValueDescription
0

The Clock Divider is not active.

Any other valueThe divided clock equals the peripheral clock divided by 2 times DIV.
The maximum bit rate is fperipheral clock/2. The minimum bit rate is fperipheral clock/2 × 4095 = fperipheral clock/8190.