46.9.4 SSC Receive Frame Mode Register

This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.

Name: SSC_RFMR
Offset: 0x14
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 FSLEN_EXT[3:0]   FSEDGE 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 2322212019181716 
  FSOS[2:0]FSLEN[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
     DATNB[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 MSBF LOOPDATLEN[4:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 24 – FSEDGE Frame Sync Edge Detection

Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.

ValueNameDescription
0 POSITIVE

Positive Edge Detection

1 NEGATIVE

Negative Edge Detection

Bits 22:20 – FSOS[2:0] Receive Frame Sync Output Selection

ValueNameDescription
0 NONE

None, RF pin is an input

1 NEGATIVE

Negative Pulse, RF pin is an output

2 POSITIVE

Positive Pulse, RF pin is an output

3 LOW

Driven Low during data transfer, RF pin is an output

4 HIGH

Driven High during data transfer, RF pin is an output

5 TOGGLING

Toggling at each start of data transfer, RF pin is an output

Bits 19:16 – FSLEN[3:0] Receive Frame Sync Length

This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register.

This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.

Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Receive Clock periods.

Bits 11:8 – DATNB[3:0] Data Number per Frame

This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).

Bit 7 – MSBF Most Significant Bit First

ValueDescription
0

The lowest significant bit of the data register is sampled first in the bit stream.

1

The most significant bit of the data register is sampled first in the bit stream.

Bit 5 – LOOP Loop Mode

ValueDescription
0

Normal operating mode.

1

RD is driven by TD, RF is driven by TF and TK drives RK.

Bits 4:0 – DATLEN[4:0] Data Length

ValueDescription
0

Forbidden value (1-bit data length not supported).

Any other value The bit stream contains DATLEN + 1 data bits.