46.9.13 SSC Receive Compare 1 Register

This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.

Name: SSC_RC1R
Offset: 0x3C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 CP1[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CP1[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15:0 – CP1[15:0] Receive Compare Data 1