46.9.14 SSC Status Register
| Name: | SSC_SR |
| Offset: | 0x40 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXURWCNT[3:0] | TXFRECNT[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RXEN | TXEN | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RXSYN | TXSYN | CP1 | CP0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVRUN | RXRDY | TXEMPTY | TXRDY | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 31:28 – RXURWCNT[3:0] Receive FIFO Unread Word Count
This counter is incremented upon each load of the receive FIFO with a data from the receive shifter and decremented by each data read from SSC_RHFR.
Bits 27:24 – TXFRECNT[3:0] Transmit FIFO Free Entries Count
This counter is decremented by each data write into SSC_THFR and incremented upon each transfer of a transmit FIFO data into the transmit shifter.
Bit 17 – RXEN Receive Enable
| Value | Description |
|---|---|
| 0 | Receive is disabled. |
| 1 | Receive is enabled. |
Bit 16 – TXEN Transmit Enable
| Value | Description |
|---|---|
| 0 | Transmit is disabled. |
| 1 | Transmit is enabled. |
Bit 11 – RXSYN Receive Sync
| Value | Description |
|---|---|
| 0 | No Rx Sync has occurred since the last read of the Status register. |
| 1 | An Rx Sync has occurred since the last read of the Status register. |
Bit 10 – TXSYN Transmit Sync
| Value | Description |
|---|---|
| 0 | No Tx Sync has occurred since the last read of the Status register. |
| 1 | A Tx Sync has occurred since the last read of the Status register. |
Bit 9 – CP1 Compare 1
| Value | Description |
|---|---|
| 0 | No compare 1 has occurred since the last read of the Status register. |
| 1 | A compare 1 has occurred since the last read of the Status register. |
Bit 8 – CP0 Compare 0
| Value | Description |
|---|---|
| 0 | No compare 0 has occurred since the last read of the Status register. |
| 1 | A compare 0 has occurred since the last read of the Status register. |
Bit 5 – OVRUN Receive Overrun
| Value | Description |
|---|---|
| 0 | No data has been loaded in SSC_RHFR while previous data has not been read since the last read of the Status Register. |
| 1 | Data has been loaded in SSC_RHFR while previous data has not yet been read since the last read of the Status Register. |
Bit 4 – RXRDY Receive Ready
| Value | Description |
|---|---|
| 0 | SSC_RHFR is empty. |
| 1 | Data has been received and loaded in SSC_RHFR. |
Bit 1 – TXEMPTY Transmit Empty
| Value | Description |
|---|---|
| 0 | Data remains in SSC_THFR or is currently transmitted from TSR. |
| 1 | Last data written in SSC_THFR has been loaded in TSR and last data loaded in TSR has been transmitted. |
Bit 0 – TXRDY Transmit Ready
| Value | Description |
|---|---|
| 0 | Data has been loaded in SSC_THFR and is waiting to be loaded in the Transmit Shift register (TSR). |
| 1 | SSC_THFR is empty. |