23.5.11 DWDT Programmable Secure Watchdog Timer Mode Register
Write access to this register has no effect if the LOCKMR command is issued in PS_WDT_CR (unlocked on hardware reset).
The PS_WDT_MR register values must not be modified within three MD_SLCK periods following a restart of the watchdog performed by a write access in PS_WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected.
| Name: | PS_WDT_MR |
| Offset: | 0x1184 |
| Reset: | 0x00000030 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WDDBGHLT | WDIDLEHLT | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WDDIS | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RPTHRST | PERIODRST | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 1 |
Bit 29 – WDDBGHLT Watchdog Debug Halt
| Value | Description |
|---|---|
| 0 | The watchdog runs when the processor is in Debug state. |
| 1 | The watchdog stops when the processor is in Debug state. |
Bit 28 – WDIDLEHLT Watchdog Idle Halt
| Value | Description |
|---|---|
| 0 | The watchdog runs when the system is in Idle state. |
| 1 | The watchdog stops when the system is in Idle state. |
Bit 12 – WDDIS Watchdog Disable
| Value | Description |
|---|---|
| 0 | Enables the Watchdog Timer. |
| 1 | Disables the Watchdog Timer. |
Bit 5 – RPTHRST Repeat Threshold Reset
| Value | Description |
|---|---|
| 0 | No reset is generated if the watchdog is restarted before the RPTH threshold |
| 1 | A reset is generated if the watchdog is restarted before the RPTH threshold |
Bit 4 – PERIODRST Period Reset
| Value | Description |
|---|---|
| 0 | No reset is generated if the watchdog down counter reaches 0 |
| 1 | A reset is generated once the watchdog down counter reaches 0 |