23.5.12 DWDT Programmable Secure Watchdog Timer Value Register
| Name: | PS_WDT_VR |
| Offset: | 0x1188 |
| Reset: | 0x00000FFF |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COUNTER[11:8] | |||||||||
| Access | R | R | R | R | |||||
| Reset | 1 | 1 | 1 | 1 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COUNTER[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 11:0 – COUNTER[11:0] Watchdog Down Counter Value
Current value of the watchdog down counter.
Due to the asynchronous operation of the DWDT with respect to the rest of the chip, to be certain that the value read in this is valid and stable, it is necessary to read this register twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required.