8.4.8.2 Basic Programming Guidelines

The Configure Watchdog period is the time for a watchdog to generate an alarm or a system reset from the last counter reload. Note that watchdogs count on slow_clock/128, so the period step is about 4 ms.

The Configure Watchdog Interrupt level is the time for a watchdog to generate a “force” interrupt from the last counter reload. This time is necessarily shorter than the watchdog period. The interrupt level step is the same as the period step.

There are two PIT counters, one secure and one non-secure. These counters must be configured in a Continuous Interrupt mode, with a period shorter than the watchdog interrupt level. Note that PITs count on the system clock, so the step depends on the selected clock scheme.

PS_WDT must be configured to generate a reset or not when the counter underflows.

Security module TZWDT protection must be configured to erase or not the secure RAM in case of PS_WDT counter underflow.

PS_WDT and NS_WDT level interrupts (“force” interrupts) must be configured.

After a watchdog system reset, RSTC_SR can be read to get the watchdog reset flag. This register must be read before the watchdog reset event, since it only reports the reset event following the last read.