74.6.3.1 DDR I/O Calibration

The DDR2/DDR3/LPDDR2/LPDDR3/DDR3L I/Os embed an automatic impedance matching control to avoid overshoots and reach the best performance levels depending on the bus load and external memories. A serial termination connection scheme, where the driver has an output impedance matched to the characteristic impedance of the line, is used to improve signal quality and reduce EMI.

One specific analog input, DDR_ZQ, is used to calibrate all DDR IOs with the external resistor RZQ = 240 Ω ±1%.

The UDDRC supports the ZQ calibration procedure used to calibrate the device DDR I/O drive strength and the commands to setup the external DDR device drive strength (refer to the section Universal DDR Memory Controller (UDDRC). The calibration cell supports all the memory types listed above.